Memory Management Unit
If the paged MMU is disabled (the E-bit in the TCR register is clear) and the TTRs are dis-
abled or do not match, then the status and protection attributes are defined by the default
translation bits (DCO, DUO, DWO, DCI, and DUI) in the TCR.
If the paged MMU is enabled (the E-bit in the TCR is set), the instruction and data MMUs
process translations by first comparing the logical address and privilege mode with the
parameters of the TTRs if they are enabled. If there is a match, the MMU uses the logical
address as a physical address for the access. If there is no match, the MMU compares the
logical address and privilege mode with the tag portions of the entries in the ATC and uses
the corresponding physical address for the access when a match occurs. When neither a
TTR nor a valid ATC entry matches, the MMU initiates a table search operation to obtain the
corresponding physical address from the translation table. When a table search is required,
the processor suspends instruction execution activity and, at the end of a successful table
search, stores the address mapping in the appropriate ATC and retries the access. The
MMU creates a valid ATC entry for the logical address. If the table search encounters an
invalid descriptor, or a write-protect for a write, or is a user access and encounters a super-
visor-only flag, then the access error exception is taken whenever the access is needed
(immediately for operands and deferred for instruction fetches).
If a write or locked read-modify-write access results in an ATC hit but the page is write pro-
tected, the access is aborted, and an access error exception is taken. If the page is not write
protected and the modified bit of the ATC entry is clear, a table search proceeds to set the
modified bit in both the page descriptor in memory and in the ATC; the access is retried. The
ATC provides the address translation for the access if the modified bit of the ATC entry is
set for a write or locked read-modify-write access to an unprotected page and if none of the
TTRs (instruction or data, as appropriate) match.
Figure 4-21 illustrates a general flowchart for address translation. The top branch of the flow-
chart applies to transparent translation. The bottom three branches apply to ATC translation.
The following paragraph describes how the MMU is affected by the RSTI and MDIS pins.
4.6.1 Effect of RSTI on the MMUs
When the MC68060 is reset by the assertion of the reset input signal, the E-bits of the TCR
and TTRs are cleared, disabling address translation. This reset causes logical addresses to
be passed through as physical addresses, allowing an operating system to set up the trans-
lation tables and MMU registers as required. After the translation tables and registers are
initialized, the E-bit of the TCR can be set, enabling paged address translation. While
address translation is disabled, the default TTR is used. The default TTR attribute bits are
cleared upon reset, so that immediately after assertion of RSTI the attributes will specify
write-through cachable mode, no write protection, user page attribute bits cleared, and 1/2-
cache mode disabled.
A reset of the processor does not invalidate any entries in the ATCs page size. A PFLUSH
instruction must be executed to flush all existing valid entries from the ATCs after a reset
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