Memory Management Unit
The MMU replaces an invalid entry when the ATC stores a new address translation. When
all entries in an ATC set are valid, the ATC selects a valid entry to be replaced, using a
pseudo round robin replacement algorithm. A 2-bit counter, which is incremented for each
ATC access, points to the entry to replace when an access misses in the ATC. ATC hit rates
are application and page-size dependent, but hit rates ranging from 98% to greater than
99% can be expected. These high rates are achieved because the ATCs are relatively large
(64 entries) and utilization efficiency is high with 8-Kbyte and 4-Kbyte page sizes.
Four independent TTRs (DTT0 and DTT1 in the data MMU, ITT0 and ITT1 in the instruction
MMU) define four blocks of logical address space to be translated to physical address
space. These logical address spaces must be at least 16 Mbytes and can overlap or be sep-
arate. Each TTR can be disabled and completely ignored. The following description
assumes that the TTRs are enabled.
When an MMU receives an address to be translated, the privilege mode and the eight high-
order bits of the address are compared to the logical address spaces defined by the two
TTRs for the corresponding MMU. The logical address space for each TTR is defined by an
S-field, logical base address field, and logical address mask field. The S-field allows match-
ing either user or supervisor accesses or both accesses. When a bit in the logical address
mask field is set, the corresponding bit of the logical base address is ignored in the address
comparison. Setting successively higher order bits in the address mask increases the size
of the physical address space.
The address for the current bus cycle and a TTR address match when the privilege mode
and logical base address bits are equal. Each TTR can specify write protection for the block.
When write protection is enabled for a block, write or locked read-modify-write accesses to
the block are aborted.
By appropriately configuring a TTR, flexible transparent mappings can be specified (refer to
4.1.3 Transparent Translation Registers for field identification). For instance, to transpar-
ently translate the user address space, the S-field is set to $0, and the logical address mask
is set to $FF in both an instruction and data TTR. To transparently translate supervisor
accesses of addresses $00000000–$0FFFFFFF with write protection, the logical base
address field is set to $0x, the logical address mask is set to $0F, the W-bit is set to one,
and the S-field is set to $1. It is not necessary for the mask field to specify a contiguous block
of memory. The inclusion of independent TTRs in both the instruction and data MMUs pro-
vides an exception to the merged instruction and data address space, allowing different
translations for instruction and operand accesses. Also, since the instruction memory unit is
only used for instruction prefetches, different instruction and data TTRs can cause PC rela-
tive operand fetches to be translated differently from instruction prefetches.
If either of the TTRs matched during an access to a memory unit (either instruction or data),
the access is transparently translated. If both registers match, the TT0 status bits are used
for the access. Transparent translation can also be implemented by the translation tables of
the translation tables if the physical addresses of pages are set equal to their logical
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