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Memory Management Unit
4-24 M68060 USER’S MANUAL MOTOROLA
4.3 ADDRESS TRANSLATION CACHES
The ATCs in the MMUs are four-way set-associative caches that each store 64 logical-to-
physical address translations and associated page information similar in form to the corre-
sponding page descriptors in memory. The purpose of the ATC is to provide a fast mecha-
nism for address translation by avoiding the overhead associated with a table search of the
logical-to-physical mapping of recently used logical addresses. Figure 4-19 illustrates the
organization of the ATC.
Each ATC entry consists of a physical address, attribute information from a corresponding
page descriptor, and a tag that contains a logical address and status information. Figure 4-
20, which illustrates the entry and tag fields, is followed by field definitions listed in alphabet-
ical order.
Figure 4-19. ATC Organization
3
PAGE FRAME PAGE OFFSET
MUX
MUX
MUX
2
1
COMPARATOR
0
STATUS
PA(31–13)
PA(11–0)
PA(12)
PAGE SIZE
PAGE SIZE
1
16
3
112
1
17
29
19
9
1
4
17
0
121631
HIT 3
HIT 2
HIT 1
HIT 0
HIT
HIT
DETECT
LINE SELECT
TAG ENTRY
29
F
C
SET 0
SET 1
SET 15
TAG ENTRY
SET
SELECT
2
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