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Memory Management Unit
MOTOROLA
M68060 USER’S MANUAL
4-13
4.2.2.3 DESCRIPTOR FIELD DEFINITIONS.
The field definitions for the table- and page-
level descriptors are listed in alphabetical order:
CM—Cache Mode
This field selects the cache mode and accesses serialization as follows:
00 = Cachable, Writethrough
01 = Cachable, Copyback
10 = Cache-Inhibited, Precise exception model
11 = Cache-Inhibited, Imprecise exception model
Section 5 Caches
provides detailed information on caching modes.
Descriptor Address
This 30-bit field, which contains the physical address of a page descriptor, is only used in
indirect descriptors.
G—Global
When this bit is set, it indicates the entry is global which gives the user the option of group-
ing entries as global or nonglobal for use when PFLUSHing the ATC, and has no other
meaning. PFLUSH instruction variants that specify nonglobal entries do not invalidate glo-
bal entries, even when all other selection criteria are satisfied. If these PFLUSH variants
are not used, then system software can use this bit.
M—Modified
This bit identifies a page which has been written to by the processor. The MC68060 sets
the M-bit in the corresponding page descriptor before a write operation to a page for which
the M-bit is clear, except for write-protect or supervisor violations in which case the M-bit
is not set. The read portion of a locked read-modify-write access is considered a write for
updating purposes. The MC68060 never clears this bit.
PDT—Page Descriptor Type
This field identifies the descriptor as an invalid descriptor, a page descriptor for a resident
page, or an indirect pointer to another page descriptor.
00 = Invalid
This code indicates that the descriptor is invalid. An invalid descriptor can repre-
sent a nonresident page or a logical address range that is out of bounds. All other
bits in the descriptor are ignored. When an invalid descriptor is encountered, an
ATC entry is not created.
01 or 11 = Resident
These codes indicate that the page is resident.
10 = Indirect
This code indicates that the descriptor is an indirect descriptor. Bits 31–2 contain
the physical address of the page descriptor. This encoding is invalid for a page
descriptor pointed to by an indirect descriptor (that is, only one level of indirection
is allowed).
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