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Memory Management Unit
MOTOROLA
M68060 USER’S MANUAL
4-5
FITC—1/2-Cache Mode (Instruction ATC)
0 = The instruction ATC operates with 64 entries.
1 = The instruction ATC operates with 32 entries.
DCO—Default Cache Mode (Data Cache)
00 = Writethrough, cachable
01 = Copyback, cachable
10 = Cache-inhibited, precise exception model
11 = Cache-inhibited, imprecise exception model
DUO—Default UPA bits (Data Cache)
These bits are two user-defined bits for operand accesses (see
4.2.2.3 Descriptor Field
Definitions
).
DWO—Default Write Protect (Data Cache)
0 = Reads and writes are allowed.
1 = Reads are allowed, writes cause a protection exception.
DCI—Default Cache Mode (Instruction Cache)
00 = Writethrough, cachable
01 = Copyback, cachable
10 = Cache-inhibited, precise exception model
11 = Cache-inhibited, imprecise exception model
DUI—Default UPA Bits (Instruction Cache)
These bits are two user-defined bits for instruction prefetch bus cycles (see
4.2.2.3
Descriptor Field Definitions
)
Bit 0—Reserved by Motorola. Always read as zero.
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