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Memory Management Unit
4-4
M68060 USER’S MANUAL
MOTOROLA
4.1.2 Translation Control Register
The 32-bit TCR contains control bits which select translation properties. The operating sys-
tem must flush the ATCs before enabling address translation since the TCR accesses and
reset do not flush the ATCs. All unimplemented bits of this register are read as zeros and
must always be written as zeros. The MC68060 always uses long-word transfers to access
this 32-bit register. All bits are cleared by reset. Figure 4-4 illustrates the TCR.
Bits 31–16—Reserved by Motorola. Always read as zero.
E—Enable
This bit enables and disables paged address translation.
0 = Disable
1 = Enable
A reset operation clears this bit. When translation is disabled, logical addresses are used
as physical addresses. The MMU instruction, PFLUSH, can be executed successfully
despite the state of the E-bit. If translation is disabled and an access does not match a
transparent translation register (TTR), the default attributes for the access on the TTR is
defined by the DCO, DUO, DCI, DWO, DUI (default TTR) bits in TCR.
P—Page Size
This bit selects the memory page size.
0 = 4 Kbytes
1 = 8 Kbytes
NAD—No Allocate Mode (Data ATC)
This bit freezes the data ATC in the current state, by enforcing a no-allocate policy for all
accesses. Accesses can still hit, misses will cause a table search. A write access which
finds a corresponding valid read will update the M-bit and the entry remains valid.
0 = Disabled
1 = Enable
NAI—No Allocate Mode (Instruction ATC)
This bit freezes the instruction ATC in the current state, by enforcing a no-allocate policy
for all accesses. Accesses can still hit, misses will cause a table search.
0 = Disabled
1 = Enable
FOTC—1/2-Cache Mode (Data ATC)
0 = The data ATC operates with 64 entries.
1 = The data ATC operates with 32 entries.
31 161514 13 12 11 10 9876 5 43210
0 00000000000000 0 E P NAD NAI FOTC FITC DCO DUO DWO DCI DUI 0
Figure 4-4. Translation Control Register Format
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