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MOTOROLA
M68060 USER’S MANUAL
4-1
SECTION 4
MEMORY MANAGEMENT UNIT
NOTE
This section does not apply to the MC68EC060. Refer to
Appendix B MC68EC060
for details.
The MC68060 supports a demand-paged virtual memory environment. Demand means that
programs request permission to use memory area by accessing logical addresses, and
paged means that memory is divided into blocks of equal size, called page frames. Each
page frame is divided
into pages of the same size. The operating system assigns pages to
page frames as they are required to meet the needs of the program.
The MC68060 memory management includes the following features:
Independent Instruction and Data Memory Management Units (MMUs)
32-Bit Logical Address Translation to 32-Bit Physical Address
User-Defined 2-Bit Physical Address Extension
Addresses Translated in Parallel with Indexing into Data or Instruction Cache
64-Entry Four-Way Set-Associative Address Translation Cache (ATC) for Each MMU
(128 Total Entries)
Global Bit Allowing Flushes of All Nonglobal Entries from ATCs
Selectable 4- or 8-Kbyte Page Size
Separate Supervisor and User Translation Tables
Two Independent Blocks for Each MMU Can Be Defined as Transparent (Untranslated)
Three-Level Translation Tables with Optional Indirection
Supervisor and Write Protections
History Bits Automatically Maintained in Descriptors
External Translation Disable Input Signal (MDIS) for Emulator Support
Caching Mode Selected on Page Basis
Default Transparent Translation
Default Cache Mode and User Attributes
The MMUs completely overlap address translation time with other processing activities
when the translation is resident in the corresponding ATC. ATC accesses operate in parallel
with indexing into the on-chip instruction and data caches. The MMU MDIS signal dynami-
cally disables address translation for emulation and diagnostic support.
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