M68060 USER’S MANUAL
188.8.131.52 ALTERNATE FUNCTION CODE REGISTERS.
The alternate function code regis-
ters contain 3-bit function codes. Function codes can be considered extensions of the 32-bit
logical address that optionally provides as many as eight 4-Gbyte address spaces. The pro-
cessor automatically generates function codes to select address spaces for data and pro-
grams at the user and supervisor modes. Certain instructions use the SFC and DFC
registers to specify the function codes for operations.
184.108.40.206 PROCESSOR CONFIGURATION REGISTER.
The PCR is an 32-bit register which
controls the operations of the MC68060 internal pipelines and contains a software readable
revision number. The PCR is shown in Figure 3-5.
These bits are configured with the value which identifies this device as an MC68060.
These bits are ignored when writing to the PCR.
Appendix A MC68LC060
Appendix B MC68EC060
for MC68LC060 and
MC68EC060, respectively, identification field values.
Bits 15–8—Revision Number
Bits 15–8 contain the 8-bit device revision number. The first revision is 00000000. These
bits are ignored when writing to the PCR.
EDEBUG—Enable Debug Features
When this bit is set, the MC68060 outputs internal control information on the address bus
(A31–A0) and data bus (D31–D0) during idle bus cycles. This capability is implemented
to support debug of designs that include the MC68060. When this bit is cleared, operation
proceeds in a normal manner and no internal information is output on idle bus cycles. This
bit is cleared at reset.
Bits 6–2—Reserved by Motorola for future use and must always be zero.
DFP—Disable Floating-Point Unit
When this bit is set, the on-chip FPU is disabled and any attempt to execute a floating-
point instruction generates a line F emulator exception. When this bit is cleared, the FPU
executes all floating-point instructions. This bit is cleared at reset. Note that before this bit
is set via the MOVEC instruction, an FNOP must be executed to ensure that all floating-
point exceptions are caught and handled. This would prevent unexpected floating-point
related exceptions to be reported when the FPU is re-enabled at a later time.
ESS—Enable Superscalar Dispatch
When this bit is set, the ability of the MC68060 to execute multiple instructions per
machine cycle is enabled. When this bit is cleared, the ability to execute multiple instruc-
tions per cycle is disabled and the MC68060 operates at a slower rate with lower perfor-
mance. This bit is cleared at reset.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 8 7 6 2 1 0
0000010000110000 Revision Number EDEBUG Reserved DFP ESS
Figure 3-5. Processor Configuration Register