M68060 USER’S MANUAL
The supervisor programming model consists of the registers available to the user as well as
the following control registers:
• 32-Bit Supervisor Stack Pointer (SSP, A7)
• 16-Bit Status Register (SR)
• 32-Bit Vector Base Register (VBR)
• Two 32-Bit Alternate Function Code Registers: Source Function Code (SFC) and Des-
tination Function Code (DFC)
• 32-Bit Processor Configuration Register (PCR)
The following paragraphs describe the supervisor programming model registers. Additional
information on the SSP, SR, and VBR registers can be found in
Section 8 Exception Pro-
220.127.116.11 SUPERVISOR STACK POINTER.
When the MC68060 is operating at the supervi-
sor level, instructions that use the system stack implicitly, or access address register A7
explicitly, use the SSP. The SSP is a general-purpose register and can be used as a soft-
ware stack pointer, index register, or base address register. The SSP can be used for word
and long-word operations. The initial value of the SSP is loaded from the reset exception
vector, address offset 0.
18.104.22.168 STATUS REGISTER.
The SR (see Figure 3-4) stores the processor status and
includes the CCR, the interrupt priority mask, and other control bits. In the supervisor mode,
software can access the entire SR. The control bits indicate the following states for the pro-
cessor: trace mode (T-bit), supervisor or user mode (S-bit), and master or interrupt state (M).
22.214.171.124 VECTOR BASE REGISTER.
The VBR contains the base address of the exception
vector table in memory. The displacement of an exception vector is added to the value in
this register to access the vector table. Refer to
Section 8 Exception Processing
mation on exception vectors.
Figure 3-4. Status Register
(CONDITION CODE REGISTER)
MASTER/INTERRUPT STATE EXTEND
15 14 13 12 11 10 9 8 7 56 43210