M68060 USER’S MANUAL
supervisor stack pointer (SSP) in the supervisor programming model. When the S-bit in the
status register (SR) is clear, the USP is the active stack pointer.
A subroutine call saves the program counter (PC) on the active system stack, and the return
restores the PC from the active system stack. Both the PC and the SR are saved on the
supervisor stack during the processing of exceptions and interrupts. Thus, the execution of
supervisor level code is independent of user code and the condition of the user stack. Con-
versely, user programs use the USP independently of supervisor stack requirements.
22.214.171.124 PROGRAM COUNTER.
The PC contains the address of the currently executing
instruction. During instruction execution and exception processing, the processor automat-
ically increments the contents of the PC or places a new value in the PC, as appropriate.
For some addressing modes, the PC can be used as a pointer for PC-relative addressing.
126.96.36.199 CONDITION CODE REGISTER.
The CCR is the least significant byte of the proces-
sor SR. Bits 3–0 represent a condition of a result generated by a processor operation. Bit 4,
the extend bit (X-bit), is an operand for multiprecision computations. The carry bit (C-bit) and
the X-bit are separate in the M68000 family to simplify programming techniques that use
3.2.2 Integer Unit Supervisor Programming Model
Only system programmers use the supervisor programming model (see Figure 3-3) to imple-
ment sensitive operating system functions, I/O control, and MMU subsystems. All accesses
that affect the control features of the MC68060 are in the supervisor programming model.
Thus, all application software is written to run in the user mode and migrates to the
MC68060 from any M68000 platform without modification.
Figure 3-3. Integer Unit Supervisor Programming Model
15 7 0
ALTERNATE SOURCE AND DESTINATION
FUNCTION CODE REGISTERS
SUPERVISOR STACK POINTER
VECTOR BASE REGISTER
PCR PROCESSOR CONFIGURATION REGISTER