M68060 USER’S MANUAL
The operation of the instruction fetch unit (IFU) and the OEPs are decoupled by a 96-byte
FIFO instruction buffer. The IFU prefetches instructions every processor clock cycle, stop-
ping only if the instruction buffer is full or encountering a wait condition due to instruction
fetch address translation or cache miss. The OEPs attempt to read instructions from the
instruction buffer and execute them every clock cycle, stopping only if full instruction infor-
mation is not present in the buffer or due to operand pipeline wait conditions.
3.2 INTEGER UNIT REGISTER DESCRIPTION
The following paragraphs describe the integer unit registers in the user and supervisor pro-
gramming models. Refer to
Section 4 Memory Management Unit
for details on the MMU
programming model and
Section 6 Floating-Point Unit
for details on the FPU program-
3.2.1 Integer Unit User Programming Model
Figure 3-2 illustrates the integer unit portion of the user programming model. The model is
the same as for previous M68000 family microprocessors, consisting of the following regis-
• 16 General-Purpose 32-Bit Registers (D7–D0, A7–A0)
• 32-Bit Program Counter (PC)
• 8-Bit Condition Code Register (CCR)
184.108.40.206 DATA REGISTERS (D7–D0).
Registers D7–D0 are used as data registers for bit
and bit field (1- to 32-bit), byte (8-bit), word (16-bit), long-word (32-bit), and quad-word (64-
bit) operations. These registers may also be used as index registers.
220.127.116.11 ADDRESS REGISTERS (A6–A0).
These registers can be used as software stack
pointers, index registers, or base address registers. The address registers may be used for
word and long-word operations.
18.104.22.168 USER STACK POINTER (A7).
A7 is used as a hardware stack pointer during
implicit or explicit stacking for subroutine calls and exception handling. The register desig-
nation A7 refers to the user stack pointer (USP) in the user programming model and to the
Figure 3-2. Integer Unit User Programming Model