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MOTOROLA
M68060 USER’S MANUAL
3-1
SECTION 3
INTEGER UNIT
This section describes the organization of the MC68060 integer unit and presents a brief
description of the associated registers. Refer to
Section 4 Memory Management Unit
for
details concerning the paged memory management unit (MMU) programming model and to
Section 6 Floating-Point Unit
for details concerning the floating-point unit (FPU) program-
ming model.
3.1 INTEGER UNIT EXECUTION PIPELINES
The MC68060 integer unit execution pipelines are four-stage pipelines which perform final
instruction decode, effective address calculation, and execution or integer operations. The
operand execution pipelines (OEPs) are referred to individually as the primary OEP (pOEP)
and the secondary OEP (sOEP). Figure 3-1 shows the integer unit of the MC68060.
Figure 3-1. MC68060 Integer Unit Pipeline
EXECUTION UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
CONTROLLER
DATA
ATC
DATA
CACHE
CONTROLLER
OPERAND DATA BUS
INSTRUCTION
CACHE
DATA
CACHE
FLOATING-
POINT
UNIT
B
U
S
C
O
N
T
R
O
L
L
E
R
ADDRESS
DATA
INTEGER UNIT
DECODE
DATA AVAILABLE
EA
FETCH
INT
EXECUTE
INSTRUCTION FETCH UNIT
BRANCH
CACHE INSTRUCTION
FETCH
EARLY
DECODE
INSTRUCTION
BUFFER
EA
CALCULATE
DECODE
EA
FETCH
INT
EXECUTE
EA
FETCH
WRITE-BACK
CONTROL
IA
CALCULATE
EA
CALCULATE
INSTRUCTION MEMORY UNIT
DATA MEMORY UNIT
FP
EXECUTE
pOEP sOEP
OC OC OC
EX
EX EX
AGAG
DS DS
DA
WB
IB
IED
IC
IAG
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