Signal Description
for one full BCLK cycle and then three-stated one BCLK cycle after the address bus is idled.
If LOCKE was already negated in the BCLK cycle in which the MC68060 relinquishes the
bus, it will be three-stated in the same BCLK cycle the address bus is idled.
LOCKE is provided to help make the MC68060 bus compatible with the MC68040-style bus
protocol; however, for new designs, external bus arbitration logic can be simplified with the
use of BGR instead of LOCKE.
Do not use LOCKE. The LOCKE protocol breaks the integrity of the locked read-modify-
write sequence if it is possible to retry the last write of a read-modify-write operation. The
reason is that when LOCKE is asserted, a bus arbiter can grant the bus to an alternate mas-
ter when the current bus cycle is finished (before the retry is attempted). The bus is arbi-
trated away, the last write’s retry is deferred until the bus is returned to the processor. In the
meantime, the alternate master can access the same location where the write should have
taken place. Hence, the integrity of the locked read-modify-write sequence is compromised
in this situation.
2.3.9 Cache Inhibit Out (CIOUT)
When asserted, this three-state output indicates that the MC68060 will not cache the current
bus information in its internal caches. Refer to
Section 4 Memory Management Unit
more information on CIOUT function. When the MC68060 is not the bus master, the CIOUT
signal is placed in a high-impedance state.
2.3.10 Byte Select Lines (BS3–BS0)
These three-state outputs indicate which bytes within a long-word transfer are being
selected and which bytes of the data bus will be used for the transfer. BS0 refers to D31–
D24, BS1 refers to D23–D16, BS2 refers to D15–D8, and BS3 refers to D7–D0. These sig-
nals are generated to provide byte data select signals which are decoded from the SIZx, A1,
and A0 signals as shown in Table 2-6. These signals are placed in a high-impedance state
when the MC68060 is not the bus master.
The following signals provide control functions for bus cycles when the MC68060 is the bus
master. Refer to
Section 7 Bus Operation
for detailed information about the relationship
of the bus cycle control signals to bus operation.
Table 2-6. Data Bus Byte Select Signals
Transfer Size SIZ1 SIZ0 A1 A0 BS0 BS1 BS2 BS3
D31–D24 D23–D16 D15–D8 D7–D0
Byte 0100 0111
Byte 0101 1011
Byte 0110 1101
Byte 0111 1110
Word 1000 0011
Word 1010 1100
Long Word 0 0 x x 0000
Line 1 1 x x 0000
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