Signal Description
Transfer Retry Acknowl-
edge TRA Indicates the need to rerun the bus cycle.
Transfer Error Acknowl-
edge TEA Indicates an error condition exists for a bus transfer.
Transfer Cycle Burst In-
hibit TBI Indicates the slave cannot handle a line burst access.
Transfer Cache Inhibit TCI Indicates the current bus transfer should not be cached.
Snoop Control SNOOP Indicates the MC68060 should snoop bus activity while it is not the bus master.
Bus Request BR Asserted by the processor to request bus mastership.
Bus Grant BG Asserted by an arbiter to grant bus mastership privileges to the processor.
Bus Grant Relinquish
Control BGR Qualifies BG by indicating the degree of necessity for relinquishing bus owner-
ship when BG is negated.
Bus Tenure Termination BTT Indicates the MC68060 has relinquished the bus in response to the external ar-
biter’s negation of BG.
Bus Busy BB Asserted by the current bus master to indicate it has assumed ownership of the
Cache Disable CDIS Dynamically disables the internal caches to assist emulator support.
MMU Disable MDIS Disables the translation mechanism of the MMUs.
Reset In RSTI Processor reset.
Reset Out RSTO Asserted during execution of a RESET instruction to reset external devices.
Interrupt Priority Level IPL2–IPL0 Provides an encoded interrupt level to the processor.
Interrupt Pending IPEND Indicates an interrupt is pending.
Autovector AVEC Used during an interrupt acknowledge transfer to request internal generation of
the vector number.
Processor Status PST4–PST0 Indicates internal processor status.
Processor Clock CLK Clock input used for all internal logic timing.
Clock Enable CLKEN Defines the speed of the system bus clock to be full, 1/2, or 1/4 the speed of the
processor clock.
JTAG Enable JTAG Selects between IEEE 1149.1 compliance operation and emulation mode oper-
Test Clock TCK Clock signal for the IEEE P1149.1 test access port (TAP).
Test Mode Select TMS Selects the principal operations of the test-support circuitry.
Test Data Input TDI Serial data input for the TAP.
Test Data Output TDO Serial data output for the TAP.
Test Reset TRST Provides an asynchronous reset of the TAP controller.
Thermal Resistor Con-
nections THERM1,
THERM0 Provides thermal sensing information.
Power Supply VCC Power supply.
Ground GND Ground connection.
Table 2-1. Signal Index (Continued)
Signal Name Mnemonic Function
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