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MOTOROLA
M68060 USER’S MANUAL
2-1
SECTION 2
SIGNAL DESCRIPTION
This section contains brief descriptions of the MC68060 signals in their functional groups
(see Figure 2-1). Each signal’s function is briefly explained, referencing other sections con-
taining detailed information about the signal and related operations. Table 2-1 lists the
MC68060 signal names, mnemonics, and functional descriptions of the signals. Timing
specifications for these signals can be found in
Section 12 Electrical and Thermal Char-
acteristics
.
NOTE
Assertion
and
negation
are used to specify forcing a signal to a
particular state.
Assertion
and
assert
refer to a signal that is ac-
tive or true.
Negation
and
negate
refer to a signal that is inactive
or false. These terms are used independently of the voltage level
(high or low) that they represent.
Table 2-1. Signal Index
Signal Name Mnemonic Function
Address Bus A31–A0 32-bit address bus used to address any of 4-Gbytes.
Cycle Long-Word Ad-
dress CLA Controls the operation of A3 and A2 during bus cycles.
Data Bus D31–D0 32-bit data bus used to transfer up to 32 bits of data per bus transfer.
Transfer Type TT1,TT0 Indicates the general transfer type: normal, MOVE16, alternate logical function
code, and acknowledge.
Transfer Modifier TM2–TM0 Indicates supplemental information about the access.
Transfer Line Number TLN1,TLN0 Indicates which cache line in a set is being pushed or loaded by the current line
transfer cycle.
User-Programmable
Attributes UPA1,UPA0 User-defined signals, controlled by the corresponding user attribute bits from the
address translation entry.
Read/Write R/W Identifies the transfer as a read or write.
Transfer Size SIZ1,SIZ0 Indicates the data transfer size. These signals, together with A0 and A1,
define the active sections of the data bus. Alternately, BS3–BS0 can be used for
this function.
Bus Lock LOCK Indicates a bus cycle is part of a read-modify-write operation and that the
sequence of bus cycles should not be interrupted.
Bus Lock End LOCKE Indicates the current bus cycle is the last in a locked sequence of bus cycles.
Cache Inhibit Out CIOUT Indicates the processor will not cache the current bus transfer information.
Byte Select BS3–BS0 Indicate which bytes within a long word are selected and which data bus bytes
are valid.
Transfer Start TS Indicates the beginning of a bus cycle.
Transfer in Progress TIP Asserted for the duration of a bus cycle.
Starting Termination Ac-
knowledge Signal Sam-
pling SAS Indicates the MC68060 will begin sampling the termination acknowledge signals.
Transfer Acknowledge TA Asserted to acknowledge a bus transfer.
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