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1
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Acronym List
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Table of Contents
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List of Illustrations
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List of Tables
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Sec. 1- Introduction
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1.1 Differences Among M68060 Family Members
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1.2 Features
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1.4 Processor Overview
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1.4.2 Integer Unit
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1.5 Processing States
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1.6 Programming Model
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1.7 Data Format Sumamry
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1.9 Instruction Set Overview
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1.10 Notational Conventions
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Sec. 2 - Signal Description
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2.1 Address and Control Signals
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2.1.2 Cycle Long-Word Address
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2.3.3 Transfer Line Number
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2.3.5 Read/Write
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2.3.9 Cache Inhibit Out
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2.4.1 Transfer Start
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2.5.3 Transfer Error Acknowledge
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2.7 Arbitration Signals
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2.7.5 Bus Busy
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2.8.2 MMU Disable
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2.9.3 Autovector
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2.10.2 MC68060 Processor Clock
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2.11 Test Signals
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2.11.4 Test Data In
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Sec. 3- Integer Unit
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3.2 Integer Unit Register Description
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3.2.2 Integer Unit Supervisor Programming Model
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Sec. 4- Memory Management Unit
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4.1 Memory Management Programming Model
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4.1.2 Translation Control Register
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4.1.3 Transparent Translation Registers
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4.2 Logical Address Translation
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4.2.2 Descriptors
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4.2.3 Translation Table Example
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4.2.4 Variations in Translation Table Structure
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4.2.5 Table Search Accesses
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4.2.6 Address Translation Protection
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4.3 Address Translation Caches
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4.4 Transparent Translation
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4.5 Address Translation summary
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4.6.2 Effect of MDIS on Address Translation
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Sec. 5- Caches
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5.2 Cache Control Register
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5.3 Cache Management
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5.4 Caching Modes
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5.4.2 Cache-Inhibited Accesses
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5.4.3 Special Accesses
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5.5.3 Read Hit
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5.7 Memory Accesses for Cache Maintenance
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5.7.2 Cache Pushes
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5.9 Store Buffer
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5.12 Cache Operation Summary
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5.12.2 Data Cache
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Sec. 6- Floating-Point Unit
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6.1 Floating-Point User Programming Model
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6.1.1 Floating-Point Data Registers
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6.1.3 Floating-Point Status Register
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6.1.4 Floating-Point Instruction Address Register
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6.3 Computational Accuracy
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6.3.1 Intermediate Result
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6.3.2 Rounding the Result
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6.4 Postprocessing Operation
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6.4.2 Conditional Testing
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6.5 Floating-Point Exceptions
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6.5.2 Unsupported Floating-Point Data Types
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6.5.3 Unimplemented Effective Address Exception
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6.6.1 Branch/Set on Unordered
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6.6.2 Signaling Not-a-Number
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6.6.3 Operand Error
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6.6.4 Overflow
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6.6.5 Underflow
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6.6.6 Divide-By-Zero
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6.6.7 Inexact Result
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6.7 Floating-Point State Frames
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Sec. 7- Bus Operation
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7.2 Full-, Half-, and Quarter-Speed Bus Operation and BCLK
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7.3 Acknowledge Termination Ignore State Capability
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7.5 Data Transfer Mechanism
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7.6 Misaligned Operands
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7.7 Processor Data Transfers
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7.7.2 Line Read Transfer
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7.7.3 Byte, Word, and Long-Word Write Cycles
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7.7.4 Line Write Cycles
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7.7.5 Locked Read-Modify-Write Cycles
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7.7.6 Emulating CAS2 and CAS Misaligned
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7.7.7 Using CLA in Increment A3 and A2
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7.8.2 Breakpoint Acknowledge Cycle
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7.9 Bus Exception Control Cycles
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7.9.2 Retry Operation
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7.9.3 Double Bus Fault
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7.10 Bus Synchronization
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7.11.1 MC68040-Arbitration Protocol
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7.11.2 MC68060-Arbitration Protocol
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7.11.3 External Arbiter Considerations
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7.12 Bus Snooping Operation
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7.13 Reset Operation
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7.14 Special Modes of Operation
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7.14.2 Acknowledge Termiation Protocol
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Sec. 8- Exception Processing
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8.2 Integer Unit Exceptions
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8.2.1 Access Error Exception
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8.2.2 Address Error Exception
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8.2.4 Illegal Instruction and Unimplemented Instruction Exceptions
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8.2.5 Privilege Violation Exception
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8.2.7 Format Error Exception
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8.2.9 Interrupt Exception
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8.2.10 Reset Exception
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8.3 Exception Priorities
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8.4 Return from Exceptions
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8.4.2 Six-Word Stack Frame
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8.4.4 Eight-Word Stack Frame
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8.4.5 Recovering from an Access Error
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8.4.6 Bus Errors and Pending Memory Writes
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8.4.7 Branch Prediction Error
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Sec. 9- IEEE 1149-1 Test and Debug Pipe Control Modes
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9.1.1 Overview
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9.1.2 JTAG Instrucion Shift Register
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9.1.3 JTAG Test Data Registers
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9.1.4 Restrictions
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9.1.6 Motorola MC68060 BSDL Description
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9.2 Debug Pipe Control Mode
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9.2.1 Debug Command Interface
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9.2.2 Debug Pipe Control Mode Commands
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9.2.3 Emulator Mode
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9.3 Switching Between JTAG and Debug Pipe Control Modes of Operation
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Sec. 10- Instruction Execution Timing
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10.1.1 Dispatch Test 1: sOEP Opword and Required Extensio Words are Valid
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10.1.3 Dispatch Test 3: Allowable Effective Addressing Mode in the sOEP
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10.1.6 Dispatch Test 6: No Register Conflicts on sOEP.IEE Resources
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10.2 Timing Assumptions
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10.3 Cache and ATC Performance Degradation Times
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10.3.2 Data ATC Miss
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10.4 Effective Address Calculation Times
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10.6 Standard Instruction Execution Times
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10.7 Immediate Instruction Execution Times
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10.8 Single-Operand Instruction Execution Times
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10.9 Shift/Rotate Execution Times
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10.11 Branch Instruction Execution Times
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10.12 LEA, PEA, and MOVEM Execution Times
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10.15 FPU Instruction Execution Times
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10.16 Exception Processing Times
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Sec. 11- Applications Information
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11.1.3 Precise Vs. Imprecise Exception Mode
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11.2.2 Output Hold Time Differences
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11.2.3 Bus Arbitration
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11.2.6 Clocking
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11.2.8 Miscellaneous Pullup Resistors
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11.4 Thermal Management
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11.5 Support Devices
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Sec. 12 - Electrical and Thermal Characteristics
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12.4 DC Electrical Specifications
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12.5 Clock Input Specifications
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12.6 Output AC Timing Specifications
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12.7 Input AC Timing Specifications
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Sec. 13 - Ordering Information and Mechanical Data
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13.2.1 MC68060, MC68LC060, and MC68EC060 Pin Grid Array
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13.2.2 MC68060, MC68LC060, and MC68EC060
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13.3 Mechanical Data
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Appx. B-MC68EC060
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Appx. C- MC68060 Software Package
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C.1 Module Format
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C.2 Unimplemented Integer Instructions
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C.2.1 Integer Emulation Results
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C.2.3 Module 2: Unimplemented Integer Instruction Library
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C.3 Floating-Point Emulation Package
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C.3.1 Floating-Point Emulation Results
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C.3.2 Module 3: Full Floating-Point Kernel
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C.3.3 Module 4: Partial Floating-Point Kernel
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C.3.4 Module 5: Floating-Point Library
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C.4 Operating System Dependencies
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C.4.2 Instructions Not Recommended
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C.5 Installation Notes
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C.5.3 Release Notes and Module Offset Assignments
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C.5.4 AESOP Electronic Bulletin Board
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Appx. D- MC68060 Insturctions
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