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MC68060 Instructions
MOTOROLA M68060 USER’S MANUAL D-23
PLPA Load Physical Address PLPA
(MC68060, MC68LC060)
Operation: If Supervisor State
Then Logical Address {DFC,An} translated to Physical
Address An
Else TRAP
Assembler
Syntax: PLPAR (An)
PLPAW (An)
Attributes: Unsized
Description: Translates the logical address defined by the contents of the destination
function code register (DFC2–DFC0) and the address register (An31–An0), using full
paged MMU functionality including TTRs, and generates a 32-bit physical address,
which is loaded into An. All access error checks are performed during the translation,
including in the checks the read/write instruction type, and an access error exception
will be taken for faulting conditions.
PLPA is a privileged instruction; attempted execution in user mode will result in a priv-
ilege violation exception.
As with normal address translation activity:
If Data TTR hit
Then Use TTR translation and An stays the same
Else if E bit of TC Register = 0 or MDIS pin asserted
Then Use Default TTR translation and An stays the same
Else if E bit of TC Register =1 and MDIS pin negated and Data ATC hit
Then use ATC translation and An = Physical Address
Else if E bit of TC Register =1 and MDIS pin negated and Data ATC miss
Then Tablewalk
If Valid Page Descriptor Encountered
Then update Data ATC and An = Physical Address
Else Take Access Error Exception
EndIF
Condition Codes:
Not affected.
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