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MC68060 Instructions
MOTOROLA M68060 USER’S MANUAL D-19
LPSTOP Low-Power Stop LPSTOP
(MC68060, MC68LC060, MC68EC060)
Operation: If Supervisor State
Generate an LPSTOP Broadcast Cycle
Immediate Data SR
“10110” PST[4:0]
STOP
Else TRAP
Assembler
Syntax: LPSTOP #<data>
Attributes: Size = (Word) Privileged
Description: Moves the immediate operand into the status register (SR). The program
counter (PC) is advanced to the next instruction and the processor stops fetching and
executing instructions.
An interrupt or reset exception causes the processor to resume instruction execution
from an LPSTOP state. If an interrupt request is asserted with a higher priority than the
current priority level set by the new SR value, an interrupt exception occurs: otherwise
the interrupt request is ignored. An external reset always initiates reset exception pro-
cessing.
A trace exception occurs if the trace bit in the SR is enabled when the LPSTOP instruc-
tion begins execution.
A privilege violation is caused by attempting to clear the S-bit of the SR on LPSTOP.
The MC68060 executes the LPSTOP instruction as follows:
1. It synchronizes the pipelines.
2. An LPSTOP broadcast cycle is generated (write cycle):
TT1–TT0 = 3
TM2–TM0 = 0
SIZ1–SIZ0 = 2
31–A0 = $FFFFFFFE
D15–D0 = immediate data
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