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Introduction
1-16
M68060 USER’S MANUAL
MOTOROLA
Table 1-3. Instruction Set Summary
Opcode Operation Syntax
ABCD BCD Source + BCD Destination + X
˘
Destination ABCD Dy,Dx
ABCD –(Ay),–(Ax)
ADD Source + Destination
˘
Destination ADD <ea>,Dn
ADD Dn,<ea>
ADDA Source + Destination
˘
Destination ADDA <ea>,An
ADDI Immediate Data + Destination
˘
Destination ADDI #<data>,<ea>
ADDQ Immediate Data + Destination
˘
Destination ADDQ #<data>,<ea>
ADDX Source + Destination + X
˘
Destination ADDX Dy,Dx
ADDX –(Ay),–(Ax)
AND Source
Λ
Destination
˘
Destination AND <ea>,Dn
AND Dn,<ea>
ANDI Immediate Data
Λ
Destination
˘
Destination ANDI #<data>,<ea>
ANDI to CCR Source
Λ
CCR
˘
CCR ANDI #<data>,CCR
ANDI to SR If supervisor state
then Source
Λ
SR
˘
SR
else TRAP ANDI #<data>,SR
ASL, ASR Destination Shifted by count
˘
Destination ASd Dx,Dy
1
ASd #<data>,Dy
ASd <ea>
Bcc If condition true
then PC + dn
˘
PC Bcc <label>
BCHG ~(bit number of Destination)
˘
Z;
~(bit number of Destination)
˘
(bit number) of Destination BCHG Dn,<ea>
BCHG #<data>,<ea>
BCLR ~(bit number of Destination)
˘
Z;
0
˘
bit number of Destination BCLR Dn,<ea>
BCLR #<data>,<ea>
BFCHG ~(bit field of Destination)
˘
bit field of Destination BFCHG <ea>{offset:width}
BFCLR 0 ˘ bit field of Destination BFCLR <ea>{offset:width}
BFEXTS bit field of Source ˘ Dn BFEXTS <ea>{offset:width},Dn
BFEXTU bit offset of Source ˘ Dn BFEXTU <ea>{offset:width},Dn
BFFFO bit offset of Source Bit Scan ˘ Dn BFFFO <ea>{offset:width},Dn
BFINS Dn ˘ bit field of Destination BFINS Dn,<ea>{offset:width}
BFSET 1s ˘ bit field of Destination BFSET <ea>{offset:width}
BFTST bit field of Destination BFTST <ea>{offset:width}
BKPT Run breakpoint acknowledge cycle;
TRAP as illegal instruction BKPT #<data>
BRA PC + dn ˘ PC BRA <label>
BSET ~(bit number of Destination) ˘ Z;
1 ˘ bit number of Destination BSET Dn,<ea>
BSET #<data>,<ea>
BSR SP – 4 ˘ SP; PC ˘ (SP); PC + dn ˘ PC BSR <label>
BTST –(bit number of Destination) ˘ Z; BTST Dn,<ea>
BTST #<data>,<ea>
CAS8CAS Destination – Compare Operand ˘ cc;
if Z, Update Operand ˘ Destination
else Destination ˘ Compare Operand
CAS Dc,Du,<ea>
CAS22
CAS2 Destination 1 – Compare 1 ˘ cc;
if Z, Destination 2 – Compare ˘ cc;
if Z, Update 1 ˘ Destination 1;
Update 2 ˘ Destination 2
else Destination 1 ˘ Compare 1;
Destination 2 ˘ Compare 2
CAS2 Dc1–Dc2,Du1–Du2,(Rn1)–
(Rn2)
CHK If Dn < 0 or Dn > Source
then TRAP CHK <ea>,Dn
CHK22If Rn < LB or If Rn > UB
then TRAP CHK2 <ea>,Rn
CINV If supervisor state
then invalidate selected cache lines
else TRAP
CINVL <caches>, (An)
CINVP <caches>, (An)
CINVA <caches>
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