MC68060 Software Package
system-specific solution, then the new user-generated emulation code should supply
the routines via the _real_cas()/_real_cas2() call-outs, and should then re-enter the
MC68060ISP through the entry point _isp_cas_finish() or _isp_cas2_finish() when
3. After emulation is completed, the pages which may have been “locked” from being
paged out earlier must now be “unlocked”. To accomplish this, the MC68060ISP exe-
cutes a _real_unlock_page() call-out for each operand.
For most systems, the entry-points _isp_cas() and _isp_cas2() routines should provide suf-
ficient emulation results. However, it is up to the system integrator to judge whether or not
these routines are sufficient, or that a more system-specific solution is needed. The following
is a description of some aspects of the _isp_cas() and _isp_cas2() emulation code.
1. Interrupt levels 0-6 are immediately masked. If the appropriate pages have been
paged in and have been checked for write permission in _real_lock_page(), then only
physical bus errors can occur within this code sequence. The routine restores the pre-
vious interrupt mask level upon completion of the algorithm. (Note: if a system, by de-
sign, allows level 7 interrupts to occur while emulating the CAS or CAS2 instructions,
then the operand data corruption may occur. External hardware may be added to the
system to physically mask all interrupts whenever LOCK is asserted.)
2. The operand ATC is loaded for each operand using the PLPAW instruction. In addi-
tion, any fresh cache entries corresponding to the operands are pushed from the
cache using CPUSHL instruction. Note: the MC68040 processor initiated the pushes,
if necessary, within the locked bus region. MC68060 hardware, however, pushes the
cache lines, if necessary, outside of the locked bus region for TAS and aligned CAS
instructions. The MC68060ISP emulates the MC68060 processor approach.
3. The main algorithm steps are pre-fetched into the instruction cache if the cache is en-
abled. The algorithm attempts to allow only operand data bus accesses during the
locked bus instruction sequence. This strategy reduces the number of cycles that the
LOCK signal will be asserted.
4. Before performing the read(s)/write(s), the bus LOCK signal is asserted by the emula-
tion code by using the MOVEC of the BUSCR register. All reads and writes when
LOCK is asserted will be precise. LOCK will not actually appear on the bus until the
first bus read cycle.
5. The LOCKE signal will be asserted for the final operand write of the emulation se-
6. The actual read(s)/write(s) are performed using the MOVES instruction for both user
and supervisor accesses. The system DFC is set to the appropriate mode before ex-
ecuting MOVES and PLPAW instructions.
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