M68060 USER’S MANUAL
The MC68EC060 is a derivative of the MC68060. The MC68EC060 has the same execution
unit as the MC68060, but has no FPU or paged MMU, which embedded control applications
generally do not require. Disregard information concerning the FPU and MMU when reading
this manual. The MC68EC060 is pin compatible with the MC68060. The following differenc-
es exist between the MC68EC060 and the MC68060:
• The MC68EC060 does not contain an FPU. When floating-point instructions are en-
countered, a floating-point disabled exception is taken.
• Bits 31–16 of the processor configuration register contain 0000010000110001, identi-
fying the device as an MC68LC/EC060.
• The MDIS pin name has been changed to the JS0 pin and is included for boundary scan
B.1 ADDRESS TRANSLATION DIFFERENCES
Although the MC68EC060 has no paged MMU, the four TTRs (ITT0, ITT1, DTT0, and DTT1)
and the default transparent translation (defined by certain bits in the TCR) operate normally
and can still be used to assign cache modes and supervisor and write protection for given
address ranges. All addresses can be mapped by the four TTRs and the default transparent
B.2 INSTRUCTION DIFFERENCES
The PFLUSH and PLPA instructions, the SRP and URP registers, and the E- and P-bits of
the TCR are not supported by the MC68EC060 and must not be used. Use of these instruc-
tions and registers in the MC68EC060 exhibits poor programming practice since no useful
results can be achieved. Any functional anomalies that may result from their use will require
system software modification (to remove offending instructions) to achieve proper operation.
The PLPA instruction operates normally except that when an address misses in the four
TTRs, instead of performing a table search operation, the access cache mode and write pro-
tection properties are defined by the default transparent translation bits in the TCR. The
address register contents are never changed since all addresses are always transparently
translated. The PLPA instruction can only generate an access error exception only on super-
visor or write protection violation cases. The PFLUSH instruction operates as a virtual NOP
When the MOVEC instruction is used to access the SRP and URP registers and the E- and
P-bits in the TCR, no exceptions are reported. However, those bits are undefined for the
MC68EC060 and must not be used.