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Electrical and Thermal Characteristics
MOTOROLA
M68060 USERÕS MANUAL
12-5
12.7 INPUT AC TIMING SPECIFICATIONS (V
CC
= 3.3 V
±
5%)
NOTE:
BCLK is not a pin signal name. It is a virtual bus clock where the BCLK rising edge coincides with that of CLK when
CLKEN is asserted. The BCLK falling edge is insignificant. An input timing reference to BCLK means that the specific
input transitions only on rising CLK edges when CLKEN is asserted. A timing reference to CLK means that the input
may transition off the rising CLK edge, regardless of CLKEN state.
Num Characteristic 50 MHz 66 MHz 75 MHz Unit
Min Max Min Max Min. Max.
15 Data-In Valid to BCLK (Setup) 2Ñ2Ñ2ÑnS
16 BCLK to Data-In Invalid (Hold) 2Ñ2Ñ2ÑnS
17 BCLK to Data-In High Impedance
(Read Followed by Write) Ñ11Ñ9Ñ8nS
22a TA, Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
22b TEA Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
22c TCI Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
22d TBI Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
22e TRA Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
23 BCLK to TA, TEA, TCI, TBI, TRA Invalid
(Hold) 2Ñ2Ñ2ÑnS
24 AVEC Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
25 BCLK to AVEC Invalid (Hold) 2Ñ2Ñ2ÑnS
41a BB Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
41b BG Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
41c CDIS, MDIS Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
41d IPL
»
Valid to CLK (Setup) 2Ñ2Ñ2ÑnS
41e BTT Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
41f BGR Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
42a BCLK to BB Invalid (Hold) 2Ñ2Ñ2ÑnS
42b BCLK to BG Invalid (Hold) 2Ñ2Ñ2ÑnS
42c BCLK to CDIS, MDIS Invalid (Hold) 2Ñ2Ñ2ÑnS
42d CLK to IPLx Invalid (Hold) 2Ñ2Ñ2ÑnS
42e BCLK to BTT Invalid (Hold) 2Ñ2Ñ2ÑnS
42f BCLK to BGR Invalid (Hold) 2Ñ2Ñ2ÑnS
44a Address Valid to BCLK (Setup) 2Ñ1Ñ2ÑnS
44c TT1 Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
44e SNOOP Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
45a BCLK to Address Invalid (Hold) 2Ñ2Ñ2ÑnS
45c BCLK to TT1 Invalid (Hold) 2Ñ2Ñ2ÑnS
45e BCLK to SNOOP Invalid (Hold) 2Ñ2Ñ2ÑnS
46 TS Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
47 BCLK to TS Invalid (Hold) 2Ñ2Ñ2ÑnS
49 BCLK to BB in High Impedance
(MC68060 Assumes Bus Mastership) Ñ3Ñ3Ñ3nS
51 RSTI Valid to BCLK 2Ñ2Ñ2ÑnS
52 BCLK to RSTI Invalid (hold) 2Ñ2Ñ2ÑnS
53 Mode Select Setup to BCLK (RSTI Asserted) 10 Ñ 7 Ñ 6.2 Ñ nS
54 BCLK to Mode Selects Invalid (RSTI Assert-
ed) 2Ñ2Ñ2ÑnS
64 CLA Valid to BCLK (Setup) 10 Ñ 7 Ñ 6.2 Ñ nS
65 BCLK to CLA Invalid (Hold) 2Ñ2Ñ2ÑnS
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