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Electrical and Thermal Characteristics
12-4
M68060 USERÕS MANUAL
MOTOROLA
12.6 OUTPUT AC TIMING SPECIFICATIONS (V
CC
= 3.3 V
±
5%)
NOTES:
1. Output timing is measured at the pin, assuming a capacitive load of 50 pF. A maximum load of 130 pF may be used,
however. Characterization indicates that at 130 pF loads, output propagation delays are modified as follows: 50 MHz,
Pad at V
CC
, multiply prop delay by 1.4; 50 MHz, Pad at 5.5 V, multiply prop delay by 1.6; 66 MHz, Pad at V
CC
, multiply
prop delay by 1.3; 66 MHz, pad at 5.5 V, multiply prop delay by 1.4. Exceeding the 130-pF limit on any pin may affect
long-term reliability and Motorola does not guarantee proper operation.
2. In a mixed supply system where the processor drives chips operating with 5-volt supply, the ÒPad Starts at 5.5 VÓ
column should be used, as it is possible that a three-state pin is at 5.5 volts when the processor begins to drive it.
For a non three-state pin driven by the processor or a homogeneous 3.3-volt system, the ÒPad Starts at VccÓ column
must be used. This note does not apply to spec numbers 11, 11a, 40, and 40a. Refer to Note 5 for these specs.
3. BCLK is not a pin signal name. It is a virtual bus clock where the BCLK rising edge coincides with that of CLK when
CLKEN is asserted. The BCLK falling edge is insignificant. An output timing reference to BCLK means that the spe-
cific output transitions only on rising CLK edges when CLKEN is asserted. A timing reference to CLK means that the
output may transition off the rising CLK edge, regardless of CLKEN state.
4. When the processor drives these signals from a three-stated condition, use spec 11a or 40a. Use the ÒPad Starts at
V
CC
Ó column or ÒPad Starts at 5.5 VÓ column as appropriate. Once these signals are driven, subsequent transitions
are defined by spec 11 or 40. The ÒPad Starts at 5.5 VÓ column has no entry for specs 11 and 40, since the processor
only drives up to the V
CC
level. BR is never three-stated by the processor, and therefore, spec 40a does not apply.
5. ÒPad Starts at 5.5 V" does not apply since these signals are always driven.
Num Characteristic
50 MHz 66 MHz 75 MHz
Unit
Pad
Starts
at 5.5 V
2
Pad
Starts
at V
CC
2
Pad
Starts
at 5.5 V
2
Pad
Starts
at V
CC 2
Pad
Starts
at 5.5 V
2
Pad
Starts
at V
CC
2
Min Max Min Max Min Max Min Max Min Max Min Max
11
4
BCLK to Address CIOUT, LOCK,
LOCKE, R/W, SIZx, TLN, TMx,
TTx, UPAx, BSx Valid (signal pre-
driven)
Ñ Ñ 2 12.6 Ñ Ñ 2 9.9 Ñ Ñ 1.5 8.8 nS
11a
4
BCLK to Address CIOUT, LOCK,
LOCKE, R/W, SIZx, TLN, TMx,
TTx, UPAx, BSx Valid (signal from
three-state)
2 15.4 2 13.5 2 11.8 2 10.4 1.5 10.5 1.5 9.2 nS
12 BCLK or CLK to Output Invalid
(Output Hold) 2Ð2Ð2Ð2Ð1.5Ð1.5ÐnS
13 BCLK to TS Valid 2 14.4 2 12.3 2 10.9 2 9.5 1.5 9.7 1.5 8.4 nS
14 BCLK to TIP Valid 2 15.4 2 13.5 2 11.8 2 10.4 1.5 10.5 1.5 9.2 nS
18 BCLK to Data Out Valid 2 13.5 2 13.5 2 10.4 2 10.4 1.5 9.2 1.5 9.2 nS
19 BCLK to Data Out Invalid (Output
Hold) 2Ð2Ð2Ð2Ð1.5Ð1.5ÐnS
21 BCLK to Data-Out High Impedance Ñ 12 Ñ 12 Ñ 10 Ñ 10 Ñ 8.9 Ñ 8.9 nS
38
BCLK to Address, CIOUT, LOCK,
LOCKE, R/W, SIZx, TS, TLNx,
TMx, TTx, UPAx, BSx High Imped-
ance
Ñ12Ñ12Ñ10Ñ10Ñ8.9Ñ8.9nS
39 CLK to BB, TIP High Impedance Ñ 12 Ñ 12 Ñ 10 Ñ 10 Ñ 8.9 Ñ 8.9 nS
40
4
BCLK to BR, BB Valid (Signal Pre-
driven) Ñ Ñ 2 12.6 Ñ Ñ 2 9.9 Ñ Ñ 1.5 8.8 nS
40a
4
BCLK to BB Valid (signal from
three-state) 2 15.4 2 13.5 2 11.8 2 10.4 1.5 10.5 1.5 9.2 nS
50
5
CLK to IPEND, PSTx, RSTO Valid Ñ Ñ 2 13.5 Ñ Ñ 2 10.4 Ñ Ñ 1.5 9.2 nS
57 BCLK to SAS Valid 2 15.4 2 13.5 2 11.8 2 10.4 1.5 10.5 1.5 9.2 nS
58 BCLK to SAS Invalid (Output Hold) 2Ð2Ð2Ð2Ð1.5Ð1.5ÐnS
59 BCLK to SAS High Impedance Ñ 12 Ñ 12 Ñ 10 Ñ 10 Ñ 8.9 Ñ 8.9 nS
60 BCLK to TS Invalid (Output Hold) 2Ð2Ð2Ð2Ð1.5Ð1.5ÐnS
61 BCLK to BTT Valid 2 15.4 2 13.5 2 11.8 2 10.4 1.5 10.5 1.5 9.2 nS
62 BCLK to BTT Invalid (Output Hold) 2Ð2Ð2Ð2Ð1.5Ð1.5ÐnS
63 BCLK to BTT High Impedance Ñ 12 Ñ 12 Ñ 10 Ñ 10 Ñ 8.9 Ñ 8.9 nS
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