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Applications Information
11-16 M68060 USER’S MANUAL MOTOROLA
The RAS access time determines the number of wait states needed for the first memory
access. The RAS access time is the time it takes between RAS being asserted and valid
data coming out of the DRAM. The total available time for the first access is the time
between the TS assertion and the first TA assertion. This time is equal to the clock period
multiplied by the number of primary wait states. In addition to the RAS access time, the
MC68060 input setup time and the TS to RAS propagation delay must also occur between
the TS and TA signals. The following equation represents the number of wait states required
for the primary memory access:
Wait States = (RAS propagation delay + RAS access time + Input Setup Time) / clock period
The following example assumes a RAS access time of 65 ns, an input setup time of 7 ns,
and a RAS propagation delay of 5 ns. The processor is running at 50 MHz, so the clock
period is 20 ns. The number of wait states required is (5ns + 65ns + 7ns) / 20 ns = 3.85 wait
states. Therefore 4 wait states are required.
The CAS access time and the CAS precharge time determines the number of secondary
wait states required. The CAS precharge time is the time that the CAS signal must remain
negated between assertions. The total time available for the secondary access is the time
between the first and second TA signals. This time is equal to the clock period multiplied by
the number of secondary wait states. Since CAS must toggle during this time, two CAS prop-
agation delays, the CAS precharge time, the CAS access time, and the MC68060 input
setup time must occur during this time. Typically, the CAS precharge time is less than a
clock period. Therefore an entire clock period is used to toggle CAS. This leaves one CAS
propagation delay time, a CAS access time, and the input setup time. This time must be less
than the number of wait states less one multiplied by the clock period. The following equa-
tion represents the number of wait states required for the secondary memory accesses:
Wait States = [(CAS propagation delay + CAS access time + input setup time) / clock period] + 1
The following example assumes a CAS access time of 20 ns, input setup time of 7 ns, and
a CAS propagation delay of 5 ns. The clock period is 20 ns. The number of wait states
required is [(5ns + 20ns + 7ns) / 20ns] + 1 = 2.6. Therefore three wait states are required.
This first line burst transfer is a 5:3:3:3 transfer. For the primary transfer, an extra clock is
added for the TS signal assertion.
In this example, a second line burst transfer occurs immediately following the first transfer.
If the same DRAM chips are being accessed, RAS precharge time must be considered. RAS
precharge time is the time that the RAS signal must remain high between assertions. In the
example, RAS precharge time is 65 ns. Two additional wait states need to be added after
the second TS to assure that the RAS precharge time is satisfied. Therefore, the second line
burst transfer is a 7:3:3:3 transfer.
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