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Applications Information
MOTOROLA M68060 USER’S MANUAL 11-15
11.2.8 Miscellaneous Pullup Resistors
Pullup CLA to prevent the A3 and A2 address lines from cycling on burst accesses. Pullup
TRA when MC68040 acknowledge termination mode is being used.
11.3 EXAMPLE DRAM ACCESS
When interfacing the MC68060 with dynamic random access memory (DRAM), it is neces-
sary to determine how many clocks per bus cycle will be needed for a line burst transfer.
The number of clocks per bus cycle is dependent upon the processor clock frequency and
the DRAM access times. In this example, the DRAM RAS access time, CAS access time,
RAS precharge time, and CAS precharge time are used to determine the number of clocks
per bus cycle of a DRAM access. Figure 11-11 shows two successive line burst transfers.
The CLA signal is used to cycle A3 and A2 a clock before the DRAM subsystem asserts TA.
Figure 11-10. MC68040 BCLK to CLKEN Relationship
Figure 11-11. DRAM Timing Analysis
CLK
CLKEN
BCLK
CLK
TS
TA
CLA
A3–A2
DATA
(WRITE CYCLE)
DATA
(READ CYCLE)
RAS
CAS
DRAM ADDRESS
W0 W1 W2 W3 W3
W2
W1W0
ROW C0 C1 C2 C3 C3
C2
C1
C0
ROW
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