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Applications Information
11-14 M68060 USER’S MANUAL MOTOROLA
11.2.6 Clocking
For systems which have PCLK-to-BCLK skew controlled by a phase-locked-loop (PLL)
clock generator such as the 88915 or 88916, it is possible to connect the PCLK of the
MC68040 to the MC68060 CLK input as shown in Figure 11-8. Otherwise, the MC68060
CLK must be generated by an 88915 PLL as shown in Figure 11-9.
Appropriate generation of the CLKEN signal to enable 1/2-speed operation is easily
achieved by delaying the MC68040 BCLK by 5 ns before feeding it into the CLKEN input of
the MC68060.
Be aware that a clock skew exists between CLK and BCLK. The MC88915 can only control
the skew to within 1 ns. Figure 11-10 shows the relationship between BCLK and CLKEN.
11.2.7 PSTx Encoding
PSTx signal encoding is different between the MC68060 and MC68040. This should not
affect normal applications because PSTx signals are not used for bus control logic.
Figure 11-8. Simple CLK Generation
Figure 11-9. Generic CLK Generation
BCLK CLKEN
CLK
MC68060
MC68040
EXISTING
SYSTEM
VIRTUAL MC68040
5 NS
PCLK
BCLK
CLKEN
Q0
2XQ
SYNC0
CLK
MC68060
MC68040
EXISTING
SYSTEM
FEEDBACK
VIRTUAL MC68040
5 ns
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