Loading...
Applications Information
11-12
M68060 USER’S MANUAL
MOTOROLA
A possible solution addressing both the address and write data hold time issue for slow
peripherals is to force at least one dead state between TA negation and TS assertion of the
next bus cycle. This can be achieved by arbitrating the bus away from the processor on any
long-word, word, or byte access. This forces the processor to release the bus, not begin a
new bus cycle, three-state the address bus, and three-state the data bus on write cycles.
Since the address and data buses (on writes) are three-stated and not directly driven by the
MC68060, output hold time in this solution relies on the capacitive loading of the bus to
achieve the extended hold time.
Once the dead state has been added, the bus is returned to the processor and normal oper-
ation continues. This suggested solution does not affect line (burst) accesses, which are typ-
ically cacheable and contain no I/O devices. For this reason, performance is not
compromised. In this implementation, the only signal that may be affected is BG. In this solu-
tion, BG is intercepted and combined with the dead-state inserting logic. This combined sig-
nal is then fed into the MC68060’s BG. Figure 11-7 shows the effect of BG.
Figure 11-6. MC68060 Address Hold Time
Figure 11-7. MC68060 Address Hold Time Fix
CLK
CLKEN
TA
TS
A31–A0
CS
1/2-SPEED BUS CLOCK
CLK
CLKEN
TA
TS
A[31:0]
CSX
BG
1/2-SPEED BUS CLOCK
Loading...
Terms of Use | Privacy Policy | DMCA Policy
2006-2020 Rsmanuals.com