M68060 USER’S MANUAL
System software can take advantage of the conditions described above to emulate an
MC68040-like interrupt handler implementation. The SR stored in the interrupt exception
stack frame will contain the previous value of the M-bit. Since the first instruction of the inter-
rupt handler is always executed prior to evaluating interrupts, a MOVE 0x2700,SR instruc-
tion can be used to disable interrupts immediately and permit the interrupt handler to move
the interrupt exception stack frame from the supervisor-stack-pointer (SSP)-addressed area
to an interrupt-stack-pointer (ISP)-addressed area.
18.104.22.168 INITIALIZATION CODE (RESET EXCEPTION HANDLER).
When the processor
emerges from reset, it enters the reset exception handler. Items that may be encountered in
the reset exception handler are discussed in the following paragraphs.
22.214.171.124.1 Processor Configuration Register (PCR) (MOVEC of PCR).
after reset, the MC68060 has the superscalar dispatch disabled and the floating-point unit
(FPU) enabled. The PCR may be used to set up the proper environment. The PCR is
accessed via the MOVEC instruction. Since this is a new MOVEC register on the MC68060,
existing MC68040 code does not reference the PCR.
To properly emulate the MC68EC040 or an MC68LC040 using an MC68060, the DFP bit in
the PCR must be set to disable the FPU. Disabling the FPU causes the MC68060 to create
an MC68LC040- or MC68EC040-compatible stack frame when a floating-point instruction is
encountered. With some modification, floating-point emulation software written for the
MC68LC040 and MC68EC040 that use the stack of type 4 may then be used. However,
keep in mind that there are differences in the floating-point instruction set. Also note that the
stacked effective address field is different when dealing with extended precision operands
using the post-increment or pre-decrement addressing modes.
The ESS bit in the PCR must be set to enable superscalar dispatch. Doing so will greatly
increase system performance.
The PCR also provides the EDEBUG bit to enable the new MC68060 debug feature. This
bit is not directly related to porting existing MC68040 software and should be disabled during
normal operation.The EDEBUG bit is for use in debugging hardware and software problems
with the aid of a logic analyzer. For more information, refer to
Section 9 IEEE 1149.1 Test
(JTAG) and Debug Pipe Control Modes
126.96.36.199.2 Default Transparent Translation Register (MOVEC of TCR).
provides a method of defining the cache mode, UPAx, and write protection if the logical
address accessed is not mapped by paged memory management and TTRs. For this case,
a transparent translation is done, and the cache mode, UPAx, write protection from the
translation control register (TCR) (accessed via the MOVEC instruction) is used.
The MC68060 default translation after reset is similar to that of the MC68040 (e.g., cache
mode=cacheable write-through, UPA=00, write protection off). Since existing MC68040
code probably writes zeroes to the new TCR bits, no additional work is expected for placing
the MC68060 default translation to be MC68040-like.
188.8.131.52.3 MC68060 Software Package (M68060SP).
The M68060SP replaces the instal-
lation of the MC68040 floating-point software package (M68040FPSP). Software that was