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Instruction Execution Timing
10-26 M68060 USER’S MANUAL MOTOROLA
10.16 EXCEPTION PROCESSING TIMES
Table 10-26 indicates the number of clock cycles required for exception processing. The
number of clock cycles includes the time spent in the OEP by the instruction causing the
exception, the stacking of the exception frame, the vector fetch, and the fetch of the first
instruction of the exception handler routine. The number of operand read and write cycles
is shown in parentheses (r/w).
1 Indicates the time from when RSTI is negated until the first
instruction enters the OEP.
2 For these entries, add the effective address calculation time.
3 Assumes either autovector or external vector supplied with zero
wait states.
4 For these entries, add the instruction execution time minus 1 if a
post-exception fault occurs.
Table 10-26. Exception Processing Times
Exception Execution Time
CPU Reset 45(2/0)1
Bus Error 19(1/4)
Address Error 19(1/3)
Illegal Instruction 19(1/2)
Integer Divide By Zero 20(1/3)2
CHK Instruction 20(1/3)2
TRAPV, TRAPcc Instructions 19(1/3)
Privilege Violation 19(1/2)
Trace 19(1/3)
Line A Emulator 19(1/2)
Line F Emulator 19(1/2)
Unimplemented EA 19(1/2)
Unimplemented Integer 19(1/2)
Format Error 23(1/2)
Nonsupported FP 19(1/3)
Interrupt323(1/2)
TRAP Instructions 19(1/2)
FP Branch on Unordered Condition 21(1/3)
FP Inexact Result 19(1/3)4
FP Divide By Zero 19(1/3)4
FP Underflow 19(1/3)4
FP Operand Error 19(1/3)4
FP Overflow 19(1/3)4
FP Signaling NAN 19(1/3) 4
FP Unimplemented Data Type 19(1/3)
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