Instruction Execution Timing
10-24 M68060 USER’S MANUAL MOTOROLA
10.15 FPU INSTRUCTION EXECUTION TIMES
Table 10-25 shows the number of clock cycles required for execution of the floating-point
instructions, including completion of the operation and storing of the result. The number of
operand read and write cycles is shown in parentheses (r/w).
1 For these entries, add the effective address calculation time.
2 For the CPUSH instruction, the operand write figure refers to line-sized transfers.
PLPA (ATC hit) — 15(0/0) — — —
PLPA (ATC miss) — 28(0/0) — — —
PFLUSH — 18(0/0) — — —
PFLUSHN — 18(0/0) — — —
PFLUSHAN — 33(0/0) — — —
PFLUSHA — 33(0/0) — — —
RESET — 520(0/0) — — —
STOP Word 8(0/0) — — —
SWAP Word 1(0/0) — — —
TRAPF — 1(0/0) — — —
TRAPcc — 1(0/0) — — —
TRAPV — 1(0/0) — — —
UNLK — 1(1/0) — — —
UNPK — 2(0/0) 2(1/1) — —
Table 10-25. Floating-Point Instruction Execution Times
Instruction
Effective Address, <ea>
FPn Dn (An) (An)+ –(An) (d16,An)
(d16,PC)
(d8,An,Xi∗SF)
(d8,PC,Xi∗SF)
(bd,An,XI∗SF)
(bd,PC,XI∗SF) (xxx).WL #<imm>
FABS 1(0/0) 3(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 3(1/0) 2(1/0) 2(0/0)
FDABS 1(0/0) 3(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 3(1/0) 2(1/0) 2(0/0)
FSABS 1(0/0) 3(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 3(1/0) 2(1/0) 2(0/0)
FADD 3(0/0) 5(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 5(1/0) 4(1/0) 4(0/0)
FDADD 3(0/0) 5(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 5(1/0) 4(1/0) 4(0/0)
FSADD 3(0/0) 5(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 4(1/0) 5(1/0) 4(1/0) 4(0/0)
FCMP 1(0/0) 3(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 3(1/0) 2(1/0) 2(0/0)
FDIV 37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0) 37(1/0) 38(1/0) 39(1/0) 38(1/0) 38(0/0)
FDDIV 37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0) 37(1/0) 38(1/0) 39(1/0) 38(1/0) 38(0/0)
FSDIV 37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0) 37(1/0) 38(1/0) 39(1/0) 38(1/0) 38(0/0)
FMOVE
,FPx 1(0/0) 3(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)
FDMOVE
,FPx 1(0/0) 3(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)
FSMOVE
,FPx 1(0/0) 3(0/0) 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 3(1/0) 2(1/0) 1(0/0)
FMOVE
FPy, — 3(0/0) 1(0/1) 1(0/1) 1(0/1) 1(1/0) 2(0/1) 3(0/1) 2(0/1) —
FMOVE
,FPCR — 8(0/0) 6(1/0) 6(1/0) 6(1/0) 6(1/0) 7(1/0) 8(1/0) 7(1/0) 7(0/0)
FMOVE
FPCR, — 4(0/0) 2(0/1) 2(0/1) 2(0/1) 2(1/0) 3(0/1) 4(0/1) 3(0/1) —
FINT 3(0/0) 4(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 5(1/0) 3(1/0) 3(0/0)
FINTRZ 3(0/0) 4(0/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 3(1/0) 5(1/0) 3(1/0) 3(0/0)
Table 10-24. Miscellaneous Instruction Execution Times (Continued)
Instruction Size Register Memory Reg -> Dest Source -> Reg
