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Introduction
1-8
M68060 USER’S MANUAL
MOTOROLA
1.4.2.2 INTEGER UNIT.
The integer unit contains dual integer execution pipelines, inter-
face logic to the FPU, and control logic for data written to the data cache and MMU. The
superscalar design of the dual integer execution pipelines provide for simultaneous instruc-
tion execution, which allows for processing more than one instruction during each machine
clock cycle. The net effect of this is a software invisible pipeline capable of sustained exe-
cution rates of less than one machine clock cycle per instruction for the M68000 instruction
set.
The integer unit’s control logic pulls an instruction pair from the instruction buffer every
machine clock cycle, stopping only if the instruction information is not available or if an inte-
ger execution pipeline hold condition exists. The six stages in the dual integer execution
pipelines are:
1. Decode (DS)—The instruction is fully decoded.
2. Effective Address Calculation (AG)—If the instruction calls for data from memory, the
location of the data is calculated.
3. Effective Address Fetch (OC)—Data is fetched from the memory location.
4. Integer Execution (EX)—The data is manipulated during execution.
5. Data Available (DA)—The result is available.
6. Write-Back (WB)—The resulting data is written back to on-chip caches or external
memory.
The MC68060 is optimized for most integer instructions to execute in one machine clock
cycle. If during the instruction decode stage, the instruction is determined to be a floating-
point instruction, it will be passed to the FPU after the effective address calculate stage. If
data is to be written to either the on-chip caches or external memory after instruction execu-
tion, the write-back stage holds the data until memory is ready to receive it.
1.4.2.3 FLOATING-POINT UNIT.
Floating-point math is distinguished from integer math,
which deals only with whole numbers and fixed decimal point locations. The IEEE-compat-
ible MC68060's FPU computes numeric calculations with a variable decimal point location.
Consolidating the FPU on-chip speeds up overall processing and eliminates the interfacing
overhead associated with external accelerators. The MC68060's FPU operates in parallel
with the integer unit. The FPU performs numeric calculations while the integer unit continues
integer processing.
The FPU has been optimized for the most frequently used instructions and data types to pro-
vide the highest possible performance. The FPU can also be disabled in software to reduce
system power consumption.
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