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Instruction Execution Timing
MOTOROLA M68060 USER’S MANUAL 10-23
1 For these instructions, add the effective address calculation time.
1 Add 2(1/0) cycles to the (bd,An,Xi*SF) time for a memory indirect address.
Table 10-22. Status Register (SR) Instruction Execution Times
Instruction Execution Time
ANDI to SR 12(0/0)
EORI to SR 12(0/0)
MOVE from SR 1(0/1)1
MOVE to SR 12(1/0)1
ORI to SR 5(0/0)
Table 10-23. MOVES Execution Times
MOVES Function Destination
Size (An) (An)+ –(An) (d16,An) (d8,An,XiSF) (bd,An,XiSF)1(xxx).WL
Source<SFC> -> Rn Byte, Word 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 3(1/0) 2(1/0)
Long 1(1/0) 1(1/0) 1(1/0) 1(1/0) 2(1/0) 3(1/0) 2(1/0)
Rn -> Dest <DFC> Byte, Word 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 3(0/1) 2(0/1)
Long 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 3(0/1) 2(0/1)
Table 10-24. Miscellaneous Instruction Execution Times
Instruction Size Register Memory Reg -> Dest Source -> Reg
ANDI to CCR Byte 1(0/0)
CHK Word 2(0/0) 2(1/0) 1——
Long 2(0/0) 2(1/0) 1——
CINVA — — <=17(0/0)
CINVL — — <=18(0/0)
CINVP — — <=274(0/0)
CPUSHA <=5394(0/512)2——
CPUSHL — — <=26(0/1)2——
CPUSHP <=2838(0/256)2——
EORI to CCR Byte 1(0/0)
EXG Long 1(0/0)
EXT Word 1(0/0)
Long 1(0/0)
EXTB Long 1(0/0)
LINK Word 2(0/1)
Long 2(0/1)
LPSTOP Word 15(0/1)
MOVE from CCR Word 1(0/0) 1(0/1)1——
MOVE to CCR Word 1(0/0) 1(1/0)1——
MOVE from USP Long 1(0/0)
MOVE to USP Long 2(0/0)
MOVEC (SFC,DFC,
USP,VBR,PCR) Long — 12(0/0) 11(0/0)
MOVEC (CACR,TC,
TTR,BUSCR,URP,SRP) Long — 15(0/0) 14(0/0)
NOP — 9(0/0)
ORI to CCR Byte 1(0/0)
PACK — 2(0/0) 2(1/1)
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