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Instruction Execution Timing
MOTOROLA M68060 USER’S MANUAL 10-19
10.9 SHIFT/ROTATE EXECUTION TIMES
Table 10-13 indicates the number of clock cycles required for execution of the shift and
rotate instructions. The number of operand read and write cycles is shown in parentheses
(r/w). Where indicated, the number of clock cycles and r/w cycles must be added to those
required for effective address calculation.
10.10 BIT MANIPULATION AND BIT FIELD EXECUTION TIMES
Table 10-14 and Table 10-15 indicate the number of clock cycles required for execution of
the bit manipulation instructions. The execution times for the bit field instructions is shown
in Table 10-16. The number of operand read and write cycles is shown in parentheses (r/w).
Where indicated, the number of clock cycles and r/w cycles must be added to those required
for effective address calculation.
1 For entries in this column, add the effective address calculation time. These operations
are word-size only.
1 For entries in this column, add the effective address calculation
time.
Table 10-13. Shift/Rotate Execution Times
Instruction Size Register Memory1
ASL, ASR Byte, Word 1(0/0) 1(1/1)
Long 1(0/0) —
LSL, LSR Byte, Word 1(0/0) 1(1/1)
Long 1(0/0) —
ROL, ROR Byte, Word 1(0/0) 1(1/1)
Long 1(0/0) —
ROXL, ROXR Byte, Word 1(0/0) 1(1/1)
Long 1(0/0) —
Table 10-14. Bit Manipulation (Dynamic Bit Count)
Execution Times
Instruction Size Register Memory1
BCHG Byte — 1(1/1)
Long 1(0/0)
BCLR Byte — 1(1/1)
Long 1(0/0)
BSET Byte — 1(1/1)
Long 1(0/0)
BTST Byte — 1(1/0)
Long 1(0/0)
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