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Instruction Execution Timing
10-18 M68060 USER’S MANUAL MOTOROLA
10.8 SINGLE-OPERAND INSTRUCTION EXECUTION TIMES
Table 10-11 shows the number of clock cycles required for execution of the single-operand
instructions. The number of operand reads and write cycles is shown in parentheses (r/w).
Where indicated, the number of clock cycles and r/w cycles must be added to those required
for effective address calculation.
Execution times for the CLR instruction are given in Table 10-12. The number of operand
reads and writes is shown in parentheses (r/w).
1 Add (1 + effective address calculation time) cycles for all addressing modes
except Rn, (An), (An)+, –(An), and (d16,An).
2 Add the effective address calculation time to these instructions.
1 Add 2(1/0) cycles to the (bd,An,Xi*SF) time for a memory indirect address.
Table 10-11. Single-Operand Instruction Execution Times
Instruction Size Register Memory
CAS Byte, Word1— 19(1/1)
Long1— 19(1/1)
NBCD Byte 1(0/0) 1(1/1)2
NEG Byte, Word 1(0/0) 1(1/1)2
Long 1(0/0) 1(1/1)2
NEGX Byte, Word 1(0/0) 1(1/1)2
Long 1(0/0) 1(1/1)2
NOT Byte, Word 1(0/0) 1(1/1)2
Long 1(0/0) 1(1/1)2
Scc Byte -> False 1(0/0) 1(1/1)2
Byte -> True 1(0/0) 1(1/1)2
TAS Byte 1(0/0) 17(1/1)2
TST Byte, Word 1(0/0) 1(1/0)2
Long 1(0/0) 1(1/0)2
Table 10-12. Clear (CLR) Execution Times
Size Dn A
n(An) (An)+ –(An) (d16,An) (d8,An,XiSF) (bd,An,XiSF)1(xxx).WL
Byte, Word 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
Long 1(0/0) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 1(0/1) 2(0/1) 1(0/1)
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