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Instruction Execution Timing
10-14
M68060 USER’S MANUAL
MOTOROLA
10.4 EFFECTIVE ADDRESS CALCULATION TIMES
Table 10-5 shows the number of clock cycles required to compute an instruction’s effective
address. The MC68060 address generation hardware supports the calculation of most
effective addresses within the structure of the operand execution pipeline with no additional
cycles required. The number of operand read and write cycles is shown in parentheses (r/w).
The following rules apply to any effective address calculation:
The size of the index register (Xi) and the scale factor (SF) do not affect the calculation
time for the indexed addressing modes.
The size of the absolute address (short, long) does not affect its calculation time. In sub-
sequent tables, the nomenclature “(xxx).WL” is used to denote either the absolute short
{(xxx).W} or absolute long {(xxx).L} addressing modes.
In general, the use of a memory indirect effective address adds three cycles to the instruc-
tion execution times (one cycle to process full format effective address and two cycles to
fetch the memory indirect pointer). For instructions which calculate both a source and des-
tination address (e.g., memory-to-memory moves), two effective address calculations are
performed, one for the source and another for the destination.
10.5 MOVE INSTRUCTION EXECUTION TIMES
Table 10-6 and Table 10-7 show the number of clock cycles for execution of the MOVE
instruction. The number of operand read and write cycles is shown in parentheses (r/
w).Note, if memory indirect addressing is used for a MOVE instruction, add 2(1/0) cycles for
Table 10-5. Effective Address Calculation Times
Addressing Mode Calculation
Time
Dn Data Register Direct 0(0/0)
An Address Register Direct 0(0/0)
(An) Address Register Indirect 0(0/0)
(An)+ Address Register Indirect with Postincrement 0(0/0)
–(An) Address Register Indirect with Predecrement 0(0/0)
(d16,An) Address Register Indirect with Displacement 0(0/0)
(d8,An,Xi
SF) Address Register Indirect with Index and Byte Displacement 0(0/0)
(bd,An,Xi
SF) Address Register Indirect with Index and Base (16-, 32-bit) Displacement 1(0/0)
([bd,An,Xn],od
)Memory Indirect Preindexed Mode 3(1/0)
([bd,An],Xn,od
)Memory Indirect Postindexed Mode 3(1/0)
(xxx).W Absolute Short 0(0/0)
(xxx).L Absolute Long 0(0/0)
(d16,PC) Program Counter with Displacement 0(0/0)
(d8,PC,Xi
SF) Program Counter with Index and Byte Displacement 0(0/0)
(bd,PC,XiSF) Program Counter with Index and Base (16-, 32-bit) Displacement 1(0/0)
#<data> Immediate 0(0/0)
([bd,PC,Xn],o
d) Program Counter Memory Indirect Preindexed Mode 3(1/0)
([bd,PC],Xn,o
d) Program Counter Memory Indirect Postindexed Mode 3(1/0)
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