M68060 USER’S MANUAL
The integer unit implements a subset of the MC68040 instruction set. The FPU implements
a subset of the MC68881/2 coprocessor instruction set. The instruction and data memory
manage the ATCs and the instruction and data caches. The ATCs provide on-chip stor-
age for the paged MMU’s most recently used address translations. The data and instruction
caches include the logic necessary to read, write, update, invalidate, and flush the caches.
The bus controller manages the interface between the MMUs and the external bus. Snoop
invalidation is supported to maintain cache consistency by monitoring the external bus when
the processor is not the current master.
1.4.2 Integer Unit
The MC68060’s integer unit carries out logical and arithmetic operations. The integer unit
contains an instruction fetch controller, an instruction execution controller, and a branch tar-
get cache. The superscalar design of the MC68060 provides dual execution pipelines in the
instruction execution controller, providing simultaneous execution.
The superscalar operation of the integer unit can be disabled in software, turning off the sec-
ond execution pipeline for debugging. Disabling the superscalar operation also lowers per-
formance and power consumption.
184.108.40.206 INSTRUCTION FETCH UNIT.
The instruction fetch unit contains an instruction
fetch pipeline and the logic that interfaces to the branch cache. The instruction fetch pipeline
consists of four stages, providing the ability to prefetch instructions in advance of their actual
use in the instruction execution controller. The continuous fetching of instructions keeps the
instruction execution controller busy for the greatest possible performance. Every instruction
passes through each of the four stages before entering the instruction execution controller.
The four stages in the instruction fetch pipeline are:
1. Instruction Address Calculation (IAG)—The virtual address of the instruction is deter-
2. Instruction Fetch (IC)—The instruction is fetched from memory.
3. Early Decode (IED)—The instruction is pre-decoded for pipeline control information.
4. Instruction Buffer (IB)—The instruction and its pipeline control information are buffered
until the integer execution pipeline is ready to process the instruction.
The branch cache plays a major role in achieving the performance levels of the MC68060.
The concept of the branch cache is to provide a mechanism that allows the instruction fetch
pipeline to detect and change the instruction stream before the change of flow affects the
instruction execution controller.
The branch cache is examined for a valid branch entry after each instruction fetch address
is generated in the instruction fetch pipeline. If a hit does not occur in the branch target
cache, the instruction fetch pipeline continues to fetch instructions sequentially. If a hit
occurs in the branch cache, indicating a branch taken instruction, the current instruction
stream is discarded and a new instruction stream is fetched starting at the location indicated
by the branch cache.