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Instruction Execution Timing
MOTOROLA
M68060 USER’S MANUAL
10-11
mov.l<mem>,An
<op> <ea using An>
4. The OEP is able to complete all memory accesses without any stall conditions due to
ATC or cache misses and/or operand data cache bank busy. This means all operand
data memory references produce address translation cache hits, are mapped to cach-
able pages, and produce hits in the operand data cache. Additionally, branch instruc-
tions are assumed to produce an instruction cache hit for the target address instruction
fetch.
The occurrence of any cache miss will add a specific number of cycles to the base exe-
cution time of an instruction (see
10.3 Cache and atc Performance Degradation
Times
and
10.4 Effective Address Calculation Times
).
For instructions which generate external bus cycles as part of their execution (e.g.,
MOVE16, CPUSH), a 2-1-1-1 memory system is assumed.
5. All data accesses are assumed to be aligned on the same byte boundary as the oper-
and size:
•16-bit operands aligned on 0-modulo-2 addresses
•32-bit operands aligned on 0-modulo-4 addresses
•64-bit operands aligned on 0-modulo-8 addresses
•96-bit operands aligned on 0-modulo-4 addresses
If the operand alignment fails these suggested guidelines, the reference is termed a
misaligned access. The processor is required to make multiple accesses to obtain any
misaligned operand. For copyback or writethrough pages, one processor clock cycle
must be added to the instruction execution time for a misaligned read reference. Two
clock cycles must be added for a misaligned write or read-modify-write.
6. Certain instructions perform a pipeline synchronization prior to their actual execution.
For these opcodes, the instruction enters the pOEP and then waits until the following
conditions are met:
•The instruction cache is in a quiescent state with all outstanding cache misses
completed.
•The data cache is in a quiescent state with all outstanding cache misses com-
pleted.
•The push and write buffers are empty.
•The execution of all previous instructions has completed.
Once all these conditions are satisfied, the instruction begins its actual execution.
For the instruction timings listed in the timing data, the following assumptions are made
for these pipeline synchronization instructions:
•The instruction cache is not processing any cache misses.
•The data cache is not processing any cache misses.
•The push and write buffers are empty.
•The OEP has dispatched an instruction or instruction-pair on the previous cycle.
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