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Introduction
1-6
M68060 USER’S MANUAL
MOTOROLA
The architecture of the MC68060 processor is implemented in the following major blocks:
Execution Unit
—Instruction Fetch Unit
—Integer Unit
—FPU
Memory Units
—Instruction Memory Unit
Instruction ATC
Instruction Cache
Instruction Cache Controller
—Data Memory Unit
Data ATC
Data Cache
Data Cache Controller
Bus Controller
These major units execute concurrently to maximize sustained performance. Note that the
caches reside on separate buses allowing concurrent instruction fetch, data read, and data
write operations (internal Harvard architecture).
Figure 1-1. MC68060 Block Diagram
EXECUTION UNIT
INSTRUCTION
ATC
INSTRUCTION
CACHE
CONTROLLER
DATA
ATC
DATA
CACHE
CONTROLLER
OPERAND DATA BUS
INSTRUCTION
CACHE
DATA
CACHE
FLOATING-
POINT
UNIT
B
U
S
C
O
N
T
R
O
L
L
E
R
ADDRESS
DATA
INTEGER UNIT
DECODE
DATA AVAILABLE
EA
FETCH
INT
EXECUTE
INSTRUCTION FETCH UNIT
BRANCH
CACHE INSTRUCTION
FETCH
EARLY
DECODE
INSTRUCTION
BUFFER
EA
CALCULATE
DECODE
EA
FETCH
INT
EXECUTE
EA
FETCH
WRITE-BACK
CONTROL
IA
CALCULATE
EA
CALCULATE
INSTRUCTION MEMORY UNIT
DATA MEMORY UNIT
FP
EXECUTE
pOEP sOEP
OC OC OC
EX
EX EX
AGAG
DS DS
DA
WB
IB
IED
IC
IAG
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