Instruction Execution Timing
Each compute engine has resources associated with its respective function. A generalized
model of the resources required for instruction execution can be stated as:
Instruction Resources = f(Base, Index, A, B, Address_result, Execute_result)
Base = Base address register for the AGU
Index = Index register for the AGU
A = Source operand required by the “A” side of the arithmetic/logic unit
within the integer execute engine
B = Source operand required by the “B” side of the arithmetic/logic unit
within the integer execute engine
Address_result = Result operand produced by the address generation unit
Execute_result = Result operand produced by the integer execute engine
In the MC68060 design, the dispatch algorithm is implemented by assigning a 5-bit “name”
to each resource. The name is then used to identify the exact resource required for each
instruction’s execution. The resource name may identify one of the sixteen general-purpose
machine registers (Rn) or a non-register resource (e.g., memory operand, immediate oper-
and, etc.).
The dispatch algorithm operates within the first stage of the operand execution pipeline. The
results of the resource examination must be completed within this first stage to transition the
appropriate instruction(s) into the subsequent stages of the OEPs. In particular, the dispatch
algorithm determines if resource conflicts exist between the pOEP and sOEP.
By definition of the MC68060 architecture, there are no conflicts possible on non-register
resources. This means the dispatch algorithm must detect any register resource conflicts
between the pOEP and sOEP. The sOEP resource requirements are validated through a
series of six tests. If all the tests are successful, the sOEP instruction is dispatched simulta-
neously with the pOEP instruction into the second stage of the pipeline. If any test fails, the
dispatching of the sOEP instruction is inhibited.
10.1.1 Dispatch Test 1: sOEP Opword and Required
Extension Words Are Valid
Whenever instructions are loaded into the OEP, the instruction buffer attempts to load a 16-
bit operation word and 32-bits of extension words into both the pOEP and sOEP. This test
validates that the operation word and any extension words required by the sOEP instruction
are present. If the required opword and extensions are valid, the subsequent tests may be
performed. In the event that any of the required instruction words are not valid, the instruc-
tion in the pOEP is dispatched immediately rather than delay execution waiting for instruc-
tion words for the sOEP.
10.1.2 Dispatch Test 2: Instruction Classification
The instruction set of the M68000 family can be broadly separated into two groups: standard
and non-standard instructions. Standard instructions represent the majority of the instruction
set and the basic control structure for the OEP supports these operations without any
instruction-specific control states. Conversely, the non-standard instructions represent more
complex operations and require additional hardware to control their execution within the
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