IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
9-34 M68060 USER’S MANUAL MOTOROLA
Figure 9-12. Transition from JTAG to Debug Mode Timing Diagram
2 3 4 5 6 7 8 9 10 11 12 13 14
1. Clock is shown at 2x TCK here for illustration. Any relationship may exist but 3 full rising edges of CLK should occur after JTAG
goes high and before PSHIFT or PDISABLE change.
2. When JTAG goes high, the MC68060 goes from "functional with JTAG" to "functional with DEBUG". When going to DEBUG
modes the JTAG package pins remap to:
TRST → PDISABLE
TDI → PTDI
TMS → PAPPLY
TCK → PSHIFT
3. Hold TRST = H across boundary to prevent PAPPLY.
4. Hold TMS = H across boundary to keep JTAG in TLR.
5. After the boundary, PAPPLY must be negated before PDISABLE negates.
ALL "P" signals internally negated when JTAG = low.
JTAG MUST BE IN TLR