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IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
9-32 M68060 USER’S MANUAL MOTOROLA
2. After RSTI is negated, the processor counts 16 CLKs before actually beginning the
reset exception processing. The “generate emulator interrupt” command must be
received through the debug pipe control mode within that 16-CLK window. The reset
exception is processed normally, but the fetch of the initial stack pointer and initial PC
is mapped to the alternate address space. Instruction execution begins in emulator
mode. The reset exception vector pointed to by VBR + $04 defines the entry point
within the alternate address space.
3. If a breakpoint entry into emulator mode is enabled via the debug pipe control mode,
the execution of a BKPT instruction generates an entry into emulator mode. For this
case, the processor creates a four-word stack frame (in alternate address space) with
the PC equal to the PC of the BKPT instruction and the vector offset equal to $30. VBR
+ $30 defines the entry point within the alternate address space.
4. If a trace entry into emulator mode is enabled via the debug pipe control mode, all
trace exceptions cause an entry into the emulator mode. For this case, the processor
creates the normal six-word trace exception stack frame (in alternate address space),
with PC equal to the next PC, address equal to the last PC, and vector offset equal to
$24. The trace exception vector pointed to by VBR + $24 defines the entry point within
the alternate address space.
Exit from emulator mode is performed via the execution of an RTE instruction. Note that an
RTE executed from emulator mode assumes that the stack is in the alternate address
space. Other properties of the processor while executing in the emulator mode are as fol-
lows:
MOVES instructions operate normally, using standard address translation/cache ac-
cess for these instructions. The MDIS and CDIS input pins can be used to disable ad-
dress translation and/or cache access on these instructions.
TAS, CAS, and MOVE16 instructions must not be executed in emulator mode—results
of these instructions executed in emulator mode are unpredictable (undefined).
All interrupts are ignored while the MC68060 is in emulator mode.
If memory does not respond to the alternate function code space, it is the responsibility of
the emulator to capture and save the stack frame information for its own use. The emulator
is also responsible for supplying the saved stack frame information in response to the reads
initiated by an RTE instruction (word read for SR, long-word read for PC, word read for for-
mat/vector). A unique PSTx encoding of $08 is used to identify emulator mode exception
processing.
The emulator interrupt exception is treated like other interrupts by the MC68060 processor
and is sampled for at the completion of execution of an instruction. Once an interruptible
point is encountered and the exception initiated, the processor pushes a normal exception
stack frame (storing SR, PC, and format/vector and decrementing the supervisor stack
pointer) by performing two long word writes. This is performed with emulator mode address-
ing—alternate function code space.
The emulator interrupt exception priority falls below trace and above regular interrupts in the
MC68060 exception priority list. Its exception vector number is 12 (vector offset = $30), its
stack frame is four-word (format =0), and it stores the PC of the next instruction (like other
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