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IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
MOTOROLA M68060 USER’S MANUAL 9-29
$0D
Force all the processor outputs to high-impedance state
This command causes the processor to three-state all output pins and ignore all input pins. This com-
mand does not apply to the debug command interface pins. This forces the processor into a state where
an emulator can generate system bus cycles by driving the appropriate pins. This command must be is-
sued only when the processor is halted.
$0E
Release all the processor outputs from high-impedance state
This command causes the processor to re-enable all output pins and begin sampling all the input pins.
This command must be issued only when the processor is halted.
$0F Negate the effects of the Disable commands
This command causes the processor to disable the effects of the commands from $10 to $17.
$10
Disable instruction cache
This command forces the processor to run with the instruction cache disabled. The $0F command ne-
gates the effect of this command. This command must be issued only when the processor is halted.
$11
Disable data cache
This command forces the processor to run with the data cache disabled. The $0F command negates the
effect of this command. This command must be issued only when the processor is halted.
$12
Disable instruction ATC
This command forces the processor to run with the instruction ATC disabled. The $0F command negates
the effect of this command. This command must be issued only when the processor is halted.
$13
Disable data ATC
This command forces the processor to run with the data ATC disabled. The $0F command negates the
effect of this command. This command must be issued only when the processor is halted.
$14
Disable write buffer
This command forces the processor to run with the store buffers disabled. This command operation is
equivalent to that provided by the cache control register (CACR) bit 29. The $0F command negates the
effect of this command. This command must be issued only when the processor is halted.
$15
Disable branch cache
This command forces the processor to run with the branch cache disabled. The $0F command negates
the effect of this command. This command must be issued only when the processor is halted.
$16
Disable FPU
This command forces the FPU-disabled operation. The $0F command negates the effect of this com-
mand. This command must be issued only when the processor is halted.
$17
Disable secondary OEP
This command disables superscalar operation. The $0F command negates the effect of this command.
This command must be issued only when the processor is halted.
$18
trace -> normal trace; bkpt -> normal breakpoint
Both the trace and breakpoint exceptions operate normally. This command must be issued only when
the processor is halted.
$19
trace -> normal trace; bkpt -> bkpt with emulator mode entry
The trace exception operates normally. A breakpoint exception operates using vector offset $30, in ad-
dition, the processor enters the emulator mode. This command must be issued only when the processor
is halted.
$1A
trace -> normal trace with emulator mode entry; bkpt -> normal breakpoint
The breakpoint exception operates normally. A trace exception operates normally; in addition, the pro-
cessor enters the emulator mode. This command must be issued only when the processor is halted.
$1B
trace -> normal trace with emulator mode entry; bkpt -> bkpt with emulator mode entry
The trace exception operates normally. The breakpoint exception operates using vector offset $30. In
addition, when either of these exceptions are taken, the processor enters the emulator mode. This com-
mand must be issued only when the processor is halted.
$1C–$1F Generate an emulator interrupt
Take an emulator interrupt exception.
Table 9-5. Command Summary (Continued)
Command Command Operation
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