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Introduction
MOTOROLA
M68060 USER’S MANUAL
1-5
Architectural highlights of the MC68060 include:
Four-Stage Instruction Fetch Unit (IFU)
— 64-Entry Instruction Address Translation Cache (ATC), Organized as 4-Way Set-
Associative, for Fast Virtual-to-Physical Address Translations
— 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Instruction Cache
—256-Entry, 4-Way Set-Associative, Virtually-Mapped Branch Cache, Which Predicts
the Direction of Branches Based on Their Past Execution History
—96-Byte FIFO Instruction Buffer to Allow Decoupling of the IFP and OEPs
Four-Stage Execution Pipelines Featuring Primary Pipeline (pOEP), Secondary Pipe-
line (sOEP), and Register File (RGF) Containing Program-Visible General Registers
— 64-Entry Operand Data ATC, Organized as 4-Way Set-Associative, for Fast Virtual-
to-Physical Address Translations
— 8- Kbyte, 4-Way Set-Associative, Physically-Mapped Operand Data Cache
— The Operand Data Cache Is Organized in a Banked Structure to Allow Simultaneous
Read/Write Accesses
— Integer Execute Engines Optimized to Perform Most Instruction Executions in a
Single Machine Cycle
—Floating-Point Execute Engine, with Floating-Point Register File, Optimized for Per-
formance with Extended-Precision-Wide Internal Datapaths.
—Four-Entry Store Buffer and One-Entry Push Buffer That Provide the Performance
Feature of Decoupling the Processor Pipeline from External Memory for Certain
Cache Modes of Operation.
This pipeline architecture supports extremely high data transfer rates within the MC68060
processor. The on-chip instruction and operand data caches provide 600 MBytes/sec @ 50
MHz to the pipelines, while the integer execute engines can support sustained transfer rates
of 1.2 GBytes/sec.
1.4 PROCESSOR OVERVIEW
The following paragraphs provide a general description of the MC68060.
1.4.1 Functional Blocks
Figure 1-1 illustrates a simplified block diagram of the MC68060.
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