IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
9.2.2 Debug Pipe Control Mode Commands
The following capabilities are provided by the debug pipe control mode:
Halt and restart processor execution
Forcing the processor into an emulator mode
From a halted processor state, the following additional capabilities are provided:
—Setting and resetting a non-pipelined execution mode in the processor
—Override disable processor configuration features (instruction cache, data cache,
address translation caches (ATCs), write buffer, branch cache, floating-point unit
(FPU), superscalar dispatch)
—Forcing insertion of cache and ATC control operations into the processor pipeline for
execution (CINV all for instruction cache and data cache, CPUSH all for instruction
cache and data cache, and PFLUSH all for ATCs)
—Forcing all processor outputs into and out of a high-impedance state and disable all
—Setting and resetting modes that convert trace exceptions and breakpoint instruc-
tions into emulator mode entry
Table 9-5 provides a brief summary of the command functions that are made available
through the debug pipe control mode. Most of the commands can only be issued only when
the processor is halted.
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