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IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
9-26 M68060 USER’S MANUAL MOTOROLA
Operating independently of the 5-bit shift register, the 6-bit parallel register is the command
register used by the operand execution pipeline (OEP) control logic to control processor
operations. The sixth bit of the parallel register is connected to the PDISABLE input and
bypasses the 5-bit shift register. PDISABLE should normally be driven negated at all times
to indicate that the command register is active. The other five bits of the parallel register are
each connected to a corresponding bit in the shift register. The PAPPLY input controls the
parallel register. When PAPPLY is asserted, the PDISABLE and shift register data are
latched into the parallel register, and the command is then transmitted to the OEP control
logic. Do not assert both PAPPLY and PSHIFT on the same rising CLK edge as this is inter-
preted as a “no operation”. Do not assert PAPPLY more frequently than once every other
rising CLK edge. Although most commands are five bits in length, it is not necessary to shift
in all five bits for the “generate an emulator interrupt” command. For that command, only
three bits need to be shifted in. Figure 9-11 shows a sample interface timing diagram.
Figure 9-11. Interface Timing
CLK
PTDI
PSHIFT
PAPPLY
PDISABLE
01
23 4
JTAG
SERIAL REGISTER 4 0
1
23 4
01
23
4
0
1
2
3
01
2
0
1
SERIAL REGISTER 3
SERIAL REGISTER 2
SERIAL REGISTER 1
SERIAL REGISTER 0 0
COMMAND VALID
PARALLEL REGISTER
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