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IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
MOTOROLA M68060 USER’S MANUAL 9-25
9.2.1 Debug Command Interface
Figure 9-10 illustrates the debug command interface and Table 9-4 outlines the pins needed
by the debug command interface. The debug command interface consists of a five-bit shift
register and a five-bit parallel register, with each register operating independently. To acti-
vate the debug command interface, JT
AG must be driven negated. This allows the debug
command interface to take over the regular JTAG interface and remap JTAG pin functions.
The resulting interface is fully synchronous to the CLK input.
The commands enter the debug command interface through the PTDI serial input signal into
the five-bit shift register. The shift register is controlled by the PSHIFT input. The PSHIFT
signal determines which rising CLK edge contains valid data on the PTDI input. When
asserted the PSHIFT input causes data from the PTDI input to be latched and causes inter-
nal data bits already in the shift register to be passed on to the next shift register bit. Serial
data eventually shifts out through the PTDO output. PTDO can be used as a status output
and can be used to verify that the shift register is operating properly. Do not assert both PAP-
PLY and PSHIFT on the same CLK edge as this is interpreted as a “no operation”.
Figure 9-10. Debug Command Interface Schematic
Table 9-4. Debug Command Interface Pins
Pin Name Alias Description
TCK PSHIFT Serial Shift Enable
TMS PAPPLY Command Apply Enable
TDI PTDI Serial Command Data In
TRST PDISABLE Debug Command Disable
TDO PTDO Serial Command Data Out
JTAG JTAG JTAG or Debug Select
CLK CLK Clock
MC68060 CHIP BOUNDARY
CLK
CONTROLLER
TO ALL
FLIP-FLOPS
TCK (PSHIFT)
TDI (PTDI)
JTAG
D31–D0
A31–A0
TMS (PAPPLY)
5-BIT
COMMAND
WORD
S
E
R
I
A
L
P
A
R
A
L
L
E
L
OEP
CONTROL LOGIC
COMMAND
VALID
TRST (PDISABLE)
TDO (PTDO)
BIT 4
BIT 0
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