M68060 USER’S MANUAL
translated. The PLPA instruction can only generate an access error exception only on super-
visor or write protection violation cases. The PFLUSH instruction operates as a virtual NOP
When the MOVEC instruction is used to access the SRP and URP registers and the E- and
P-bits in the TCR, no exceptions are reported. However, those bits are undefined for the
MC68EC060 and must not be used.
The main features of the MC68060 are as follows:
• 1.6–1.7 Times the MC68040 Performance at the Same Clock Rate with Existing Com-
pliers. 3.2–3.4 Times the Performance of a 25 MHZ MC68040.
• Harvard Architecture with Independent, Decoupled Fetch and Execution Pipelines.
• Branch Prediction Logic with a 256-Entry, 4-Way Set-Associative, Virtual-Mapped
Branch Cache for Improved Branch Instruction Performance.
• A Superscalar Pipeline and Dual Integer Execution Units Achieving Simultaneous, but
not Out-of-Order Instruction Execution.
• An IEEE Standard, MC68040- and MC68881-/MC68882-Compatible FPU.
• An MC68040-Compatible Paged Memory Management Unit with Dual 64-Entry
Address Translation Caches
• Dual 8-Kbyte Caches (Instruction Cache and Data Cache)
• A Flexible, High-Bandwidth Synchronous Bus Interface
• User Object-Code Compatible with All Earlier M68000 Microprocessors
The instruction fetch unit (IFU) is a four-stage pipeline for prefetching instructions. The dual
operand execution pipelines (OEPs) (named primary” (pOEP) and secondary (sOEP)) are
four-stage pipelines for decoding the instructions, fetching the required operand(s), and then
performing the actual execution of the instructions. Since the IFU and OEP are decoupled
by a first-in-first-out (FIFO) instruction buffer, the IFU is able to prefetch instructions in
advance of their actual use by the OEPs.
The MC68060 is designed to maximize the OEP’s efficiency through the use of a supersca-
lar pipeline architecture. This architectural advance improves processor performance dra-
matically by exploiting instruction-level parallelism. The term superscalar denotes the ability
to detect, dispatch, execute, and return results from more than one instruction during each
machine cycle from an otherwise conventional instruction stream.
As a result, multiple instructions may be executed in a single machine cycle. Since the dual
OEPs perform in a lock-step mode of operation, the multiple instruction execution is per-
formed simultaneously, but not out-of-order. The net effect is a software-invisible pipeline
architecture capable of sustained execution rates of < 1 machine cycle per instruction of the
M68000 instruction set.