IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
9.1.6 Motorola MC68060 BSDL Description
-- Version 1.0 02-18-94
-- Revision List: None
-- Package Type: 18 x 18 PGA
entity MC68060 is
generic(PHYSICAL_PIN_MAP:string := "PGA_18x18");
port (
TDI: in bit;
TDO: out bit;
TMS: in bit;
TCK: in bit;
TRST: in bit;
D: inout bit_vector(0 to 31);
A: inout bit_vector(0 to 31);
CLA: in bit;
TM: out bit_vector(0 to 2);
TLN: out bit_vector(0 to 1);
R_W: out bit;
SIZ: out bit_vector(0 to 1);
LOCKE: out bit;
LOCK: out bit;
BR: out bit;
BB: inout bit;
SNOOP: in bit;
TIP: out bit;
TS: inout bit;
BTT: inout bit;
SAS: out bit;
PST: out bit_vector(0 to 4);
TA: in bit;
TEA: in bit;
TRA: in bit;
BG: in bit;
BGR: in bit;
TBI: in bit;
AVEC: in bit;
TCI: in bit;
CLK: in bit;
CLKEN: in bit;
IPL: in bit_vector(0 to 2);
RSTI: in bit;
CDIS: in bit;
MDIS: in bit;
BS: out bit_vector(0 to 3);
RSTO: out bit;
IPEND: out bit;
CIOUT: out bit;
UPA: out bit_vector(0 to 1);
TT1: inout bit;
TT0: out bit;
JTAGENB: in bit_vector(0 to 2);
THERM1: linkage bit;
THERM0: linkage bit;
EVDD: linkage bit_vector(1 to 25);
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