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IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
9-16
M68060 USER’S MANUAL
MOTOROLA
A second method of using the MC68060 without the IEEE 1149.1 logic being active is to
select the alternate complementary test debug emulation mode by placing a logic 1 on the
defined compliance enable pin, JTAG. When the JTAG is asserted, then the IEEE 1149.1
test controller is placed in the test-logic-reset state by applying a logic 0 on the internal TRST
signal to the controller, and the TAP pins are remapped to their equivalent debug emulation
mode pins.
NOTE
The MC68060 supports the low-power stop mode which can iso-
late the input and output signal pins from their internal connec-
tions and allows the internal system clock to be stopped. In
accordance with IEEE1149.1, the JTAG logic can become the
chip master during this functional mode and can conduct test
operations. During this type of testing, the MC68060 will con-
sume power at a level higher than that specified for functional
LPSTOP mode. If the JTAG mode is left active, but is not being
actively used to conduct test operations, the MC68060 will con-
sume power at a level below the rated LPSTOP maximum but
not at the lowest possible level. In order to consume the least
possible power, the JTAG logic must be specifically disabled by
placing a logic 0 on the TRST pin and a logic 1 on the TMS pin,
as shown in Figure 9-9.
Figure 9-9. Circuit Disabling IEEE Standard 1149.1
TDI
TMS
TRST
TCK
TD0 NO CONNECTION
Vcc
1K
JTAG
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