IEEE 1149.1 Test (JTAG) and Debug Pipe Control Modes
An IEEE-1149.1-compliant bypass register has been
included on the MC68060. This register is a single bit in depth when connected between TDI
and TDO. The register element is in the shift path which operates during rising edges of TCK
while the TAP state machine is in the shift-DR state or captures a default state of logic 0
during the rising edge of TCK while the TAP state machine is in the capture-DR state.
9.1.4 Restrictions
The test logic is implemented using static logic design, and TCK can be stopped in either a
high or low state without loss of data. The system logic, however, operates on a different
system clock which is not synchronized to TCK internally. Any mixed operation requiring the
use of 1149.1 test logic in conjunction with system functional logic that uses both clocks,
must have coordination and synchronization of these clocks done externally to the
The MC68060 also includes an internal instruction known as LPSTOP which can place the
output pins in a high-impedance state, isolate the input pins from their internal signals, and
stop the internal clock. Special care must be taken to ensure that the JTAG logic does not
consume excess power during this mode if it is to be left inactive (see
9.1.5 Disabling the
IEEE 1149.1 Standard Operation
9.1.5 Disabling the IEEE 1149.1 Standard Operation
There are two methods by which the device can be used without the IEEE 1149.1 test logic
being active: 1) non-use of the JTAG test logic by either non-termination (disconnection) or
intentional fixing of TAP logic values, and 2) intentional disabling of the JTAG test logic by
assertion of the JTAG signal.
There are several considerations that must be addressed if the IEEE 1149.1 logic is not
going to be used once the MC68060 is assembled onto a board. The prime consideration is
to ensure that the IEEE 1149.1 test logic remains transparent and benign to the system logic
during functional operation. This requires the minimum of either connecting the TRST pin to
logic 0, or connecting the TCK clock pin to a clock source that will supply five rising edges
and the falling edge after the fifth rising edge, to ensure that the part enters the test-logic-
reset state. The recommended solution is to connect TRST to logic 0 since logic was
included to ensure that unterminated or fixed-value terminated pins consume the least
power during the LPSTOP functional state. Another consideration is that the TCK pin does
not have a pullup as is required on the TMS, TDI, and TRST pins; therefore, it should not be
left unterminated to preclude mid-level input values.
Figure 9-8. JTAG Bypass Register
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